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Instructor: Prof. Eby G. Friedman
Course Ref. No. 75467 - 4 Credit Course
Class Lectures Times
Tuesdays and Thursdays - 3:25 to 4:40 P. M. in CSB 426
Fridays - 3:00 P.M. in CSB 426
A reading course in which some of
the primary as well as recent papers in the field of VLSI digital and
analog design methodologies will be reviewed and discussed. It is expected that each
student will participate in the discussions. The focus will be to
provide background and insight into some of the most active performance
related research areas in the field of VLSI design methodologies, such
as CMOS delay and modeling,
timing and signal delay analysis, low power CMOS design and analysis,
optimal transistor sizing and buffer tapering, pipelining and
register allocation, synchronization and clock distribution, retiming,
interconnect delay, dynamic CMOS design techniques, asynchronous vs. synchronous tradeoffs, low power
design, and CMOS power dissipation.
Permission of the instructor is required to take this course.
TA: Ravi Patel: email@example.com (email for appointment)
M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer Verlag, 2008.
V. Kursun and
E. G. Friedman, Multi-Voltage CMOS Circuit Design, John Wiley &
Sons Press, 2006.
A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performanmce Microprocessor Circuits, IEEE Press, 2001
Y. I. Ismail and E. G. Friedman, On-Chip Inductance in High Speed Integrated Circuits
I. S. Kourtev and E. G. Friedman, Timing Optimization Through Clock Skew Scheduling, Kluwer Academic Publishers, 2000
Theory of CMOS Digital Circuits and Circuit Failures, Princeton
University Press, 1992.
H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.
E.G. Friedman, Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, 1995
Numerous journal and conference papers
COPYRIGHT 2001 ALL RIGHTS RESERVED