Monday, April 6, 2009
Professor Eby G. Friedman
The continuous progress in the design and manufacturing of integrated circuits (ICs) has enabled the integration of more than two billion transistors on the same die with clock frequencies well above several gigahertz. These improvements have triggered the era of system-on-chip (SoC) and system-in-package (SiP), drastically changing the classical understanding of noise in complex ICs. Traditionally, device noise has been the primary concern for analog ICs while digital ICs have typically been considered to be relatively immune to noise. This situation has changed significantly due to denser integration and faster signal transition times. Specifically, switching noise has become a primary design criterion for both mixed-signal and high performance synchronous digital ICs.
Voltage fluctuations on the power/ground nodes of a circuit, i.e., power/ground noise, is a type of switching noise affecting both mixed-signal and digital ICs. A methodology is proposed to accurately estimate the worst case power/ground noise in an inductive power/ground distribution network with a decoupling capacitor. In mixed-signal ICs, power/ground noise affects the highly sensitive analog/RF blocks through the monolithic substrate, degrading critical performance parameters such as gain, bandwidth, dynamic range, total harmonic distortion, and phase noise. Several approaches are presented to efficiently model and alleviate substrate noise coupling in mixed-signal ICs. The proposed analysis process determines the noise characteristics of a circuit, thereby identifying appropriate noise isolation techniques. A methodology is also proposed to reduce noise by incorporating noise-aware standard cells. The proposed methodologies and algorithms are validated with industrial circuits, exhibiting significant improvement in computational efficiency while maintaining sufficient accuracy in the noise voltage. A significant reduction in substrate coupling noise is also demonstrated.
In synchronous digital ICs, switching noise affects the timing characteristics of a circuit by generating additional delay uncertainty, possibly degrading system performance or causing a circuit to fail. Interdependent setup and hold times are characterized and exploited to compensate for delay uncertainty, producing a more robust circuit tolerant to switching noise. The proposed algorithms are demonstrated on industrial circuits, verifying the efficiency of exploiting interdependence in reducing delay uncertainty. The research presented in this dissertation provides methodologies and algorithms for designing both mixed-signal and synchronous digital ICs with superior noise performance and enhanced signal integrity.