Engin Ipek's Research to Center on Self-Optimizing Multicore Architectures

Recently, the Department of Electrical and Computer Engineering (ECE) welcomed Engin Ipek in a joint appointment as Assistant Professor of Electrical and Computer Engineering and Assistant Professor of Computer Science. Ipek came to us from the Computer Architecture Group of Microsoft Research, where his focus was on multicore architectures, hardware-software interaction, and the application of machine learning to computer systems.At the University, Ipek will continue developing flexible, self-optimizing multicore architectures. Basically, what this means is that the architectures are able to adapt to the needs of software running on them. As Ipek explains, "Both the initial adoption and the longevity of multicore systems hinges critically on their ability to embrace a diverse and dynamically changing software eco-system, consisting of software products with very different characteristics and in different stages of development. Unfortunately, this stands in sharp contrast to the rigid nature of existing multicore architectures, which are typically focused on optimizing average or worst-case performance, and are statically tuned to perform well over a relatively narrow application class."

An example is off-chip DRAM memory bandwidth, a key shared resource in multicore chips. Along with the growth in transistor densities comes an increase in off-chip bandwidth requirements. This makes DRAM scheduling even more challenging. Issues involve access scheduling constraints, prioritization requests, and adapting to a dynamically changing memory reference stream. Yet most current schedulers do not evolve and adapt to changing workload demands. Instead, fixed scheduling is common, and memory controllers grossly underutilize the available bandwidth.

With his team, Ipek has proposed using machine learning technology to circumvent these problems. A self-optimizing, adaptive memory controller can plan, learn, and adapt to changing workloads. Specifically, he suggests the use of reinforcement learning that enables the hardware designer to focus on the performance targets of a controller and the appropriate system variables for deriving optimal scheduling policies.

In addition, Ipek has proposed coordinated hardware mechanisms to manage other critical shared resources: on-chip last level cache space and the chip's power budget. He proposes to address these issues at run time and without prior knowledge of the workload. At run time, a machine learning-based resource management scheme monitors each application's execution and learns how to predict system performance based on allocation decisions.

Along with more efficient resource management, multicore systems also require flexibility in their execution substrates. An example, according to Ipek, is being able to change the granularity of the architecture at run time, hence accommodating software at different stages of parallelization. Ipek is also exploring ways to enable independent cores to "fuse" into one large CPU on demand. "We call this idea, core fusion," he explains. "We envision a core fusion chip as a homogeneous substrate with conventional memory coherence/consistency support, where groups of up to four adjacent cores and their i- and d-caches can be fused at run-time into CPUs that have up to four times the fetch, issue, and commit width, and up to four times the i-cache, d-cache, branch predictor, and BTB size." This method would require no additional programming or special compiler support. It would provide a single execution model across all configurations, and it would leverage mature micro-architecture technologies.

Further, dynamic reconfiguration would allow the cores to verify each other's execution. Requiring no static core binding during the design phase and requiring no dedicated communications hardware, this method would offer a few advantages. Ipek suggests that it would be possible for on-demand triple modular redundancy to overcome hardware faults, also that hardware would degrade much more slowly than mechanisms relying on static binding.

Ipek plans to extend his machine learning-based DRAM scheduling and multi-resource allocations to additional architectural control problems. Specifically, he intends to find solutions to hardware-assisted thread and task scheduling for parallel applications, adaptive cache insertion/replacement policies, prefetching, thread selection policies in multithreaded cores; dynamic energy, reliability, or quality-of-service optimization; branch or value speculation; and routing in on- and off-chip interconnects.

"Ultimately," Ipek says, "if successful, my work and the follow-up work by other researchers may cause a significant leap in the performance and flexibility of microprocessors and computer systems."

We share Assistant Professor Ipek's hopes. His credentials prove that he is a capable researcher and valuable teacher.

With numerous publications to his credit, Ipek received his PhD in Electrical and Computer Engineering from Cornell University in 2008. His doctoral dissertation was nominated by Cornell for the 2008 ACM Doctoral Dissertation Award. He earned his BS in 2003 and his MS in 2007, both from Cornell in Electrical and Computer Engineering.

Ipek has been a researcher at Microsoft since 2007. He worked as a graduate intern for Intel Corporation for a few months in 2005, and before that, served as a graduate intern at Lawrence Livermore National Laboratory for approximately half a year.

Assistant Professor Ipek has extensive experience supervising both graduate and undergraduate students, and he was a teaching assistant at Cornell for two semesters. The University of Rochester is pleased to have him onboard.