Research                   

Books and Book Chapters

[1] Q. Yu and P. Ampadu, "Transient and Permanent Error Control for Networks-on-Chip," Spinger Press, 2012.

[2] D. Wolpert and P. Ampadu, "Managing Temperature Effects in Nanoscale Adaptive Systems," Spinger Press, 2012.

[3] B. Fu and P. Ampadu, "Error Control for Network-on-Chip Links," Spinger Press, 2012.

[4] P. Ampadu, B.Fu, D. Wolpert, Q. Yu, "Adaptive Voltage Control for Energy-Efficient NoC Links," in Low-Power Networks on Chip, C. Silvano, M. Lajolo, G. Palermo, Ed. Milan: Springer Press, 2011, pp. 45-69.

Journal Papers

[5] Q. Yu and P. Ampadu, "Dual-Layer cooperative error control for reliable nanoscale networks-on-chip," IEEE Trans. Very Large Scale Integration (VLSI) Syst.,, vol. 20, no. 7, pp. 1304-1317, Jul. 2012.

[6] D. Wolpert and P. Ampadu, "Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 59, no. 4, pp. 735-748, Apr. 2012.

[7] D. Wolpert and P. Ampadu, "A sensor system to detect positive and negative temperature dependences," IEEE Trans. Circuits Syst. II: Express Briefs, vol. 58, no. 4, pp. 235-239, Apr. 2011.

[8] D. Wolpert, Q. Diduck, P. Ampadu, "NAND gate design for ballistic deflection transistors," IEEE Trans. Nanotechnology (TNANO), vol. 10, no. 1, pp. 150-154, Jan. 2011.

[9] Q. Yu and P. Ampadu, "A dual-layer method for transient and permanent error co-management in NoC links," IEEE Trans. Circuits Syst. II: Express Briefs, vol. 58, no. 1, pp. 36-40, Jan. 2011.

[10] B. Fu and P. Ampadu, "Exploiting parity computation latency for on-chip crosstalk reduction," IEEE Trans. Circuits Syst. II: Express Briefs, vol. 57, no. 5, pp. 399-403, May 2010.

[11] B. Fu and P. Ampadu, "Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects," IET Computers & Digital Techniques, vol. 4, no. 3, pp. 251-261, May 2010.

[12] T. Lehtonen, D. Wolpert, P. Liljeberg, J. Plosila, P. Ampadu, "Self-adaptive system for addressing permanent errors in on-chip interconnects," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 18, no. 4, pp. 527-540, Apr. 2010.

[13] Q. Yu and P. Ampadu, "A flexible parallel simulator for networks-on-chip with error control," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 1, pp. 103-116, Jan. 2010.

[14] Q. Yu and P. Ampadu, "Adaptive error control for nanometer scale NoC links," IET Computers & Digital Techniques - Special issue on advances in nanoelectronics circuits and systems, vol. 3, no. 6, pp. 643-659, Nov. 2009.

[15] B. Fu and P. Ampadu, "On Hamming product codes with type-II hybrid ARQ for on-chip interconnects," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 56, no. 9, pp. 2042-2054, Sep. 2009.

[16] B. Fu and P. Ampadu, "An area efficient FFT/IFFT processor for MIMO-OFDM WLAN 802.11n," J. Signal Processing Systems (JSPS), doi:10.1007/s11265-008-0264-9, pp. 1-9, Jul. 2009.

[17] D. Huo, Q. Yu, D. Wolpert, P. Ampadu, "A simulator for ballistic nanostructures in a 2-D electron gas," ACM J. Emerging Technologies in Computing Syst. (JETC), vol. 5, no. 1, pp. 5.1-5.21, Jan. 2009.

[18] D. Wolpert and P. Ampadu, "Adaptive delay correction for runtime variation in dynamic voltage scaling systems," J. of Circuits, Syst., and Computers (JCSC), vol. 17, no. 6, pp. 1111-1128, Dec. 2008.

[19] B. Fu and P. Ampadu, "An energy-efficient multi-wire error control scheme for reliable on-chip interconnects using Hamming product codes," VLSI Design, vol. 2008, doi:10.1155/2008/109490, article ID: 109490, pp. 1-14, 2008.

Conference Papers

[20] M. Zhang, Q. Yu, P. Ampadu, "Fine-grained splitting methods to address permanent errors in network-on-Chip links," Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS'12), pp. 2717-2720, May 2012.

[21] Q. Yu, J. Cano, J. Flich, P. Ampadu, "Transient and permanent error control for high-end multiprocessor systems-on-chip," Proc. 6th ACM/IEEE Int. Symp. on Networks-on-Chip (NoCS'12), pp. 169-176, May 2012.

[22] Q. Yu, M. Zhang, P. Ampadu, "Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration," Proc. 5th ACM/IEEE Int. Symp. on Networks-on-Chip (NoCS'11), pp. 105-112, May 2011.

[23] D. Wolpert and P. Ampadu, "Level shifter speed, power, and reliability trade-offs across normal and reverse temperature dependences," 53rd IEEE Int. Midwest Symp. on Circuits and Syst. (MWSCAS'10), pp. 1254-1257, Aug. 2010.

[24] Q. Yu, B. Zhang, Y. Li, P. Ampadu, "Error control integration scheme for reliable NoCs," IEEE Int. Symp. on Circuits and Syst. (ISCAS'10), pp. 3893-3896, May 2010.

[25] Q. Yu and P. Ampadu, "Transient and permanent error co-management method for reliable networks-on-chip," Proc. 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NoCS'10), pp. 145-154, May 2010.

[26] D. Wolpert, B. Fu, P. Ampadu, "Temperature-aware delay borrowing for energy-efficient low-voltage link design," Proc. 4th ACM/IEEE Int. Symp. on Networks-on-Chip (NoCS'10), pp. 107-114, May 2010.

[27] B. Fu and P. Ampadu, "Burst error detection hybrid ARQ with crosstalk-delay reduction for reliable on-chip interconnects," Proc. 24th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Syst. (DFT'09), pp. 440-448, Oct. 2009.

[28] Q. Yu and P. Ampadu, "Dual-layer cooperative error control for a reliable nanoscale NoC," Proc. 24th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Syst. (DFT'09), pp. 431-439, Oct. 2009.

[29] D. Wolpert and P. Ampadu, "A sensor to detect normal or reverse temperature dependence in nanoscale CMOS circuits," Proc. 24th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Syst. (DFT'09), pp. 193-201, Oct. 2009.

[23] V. Kaushal, G. Guarino, Q. Yu, P. Ampadu, R. Sobolewski, M. Margala, "Current transport modeling and experimental study of THz room temperature ballistic deflection transistors," Proc. 16th Int. Conf. on Electron Dynamics in Semiconductor, Optoelectronics and Nanostructures (Edison16), pp. 131, Aug. 2009.

[30] B. Fu and P. Ampadu, "A dual-mode hybrid ARQ scheme for energy efficient on-chip interconnects," Springer Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering - 3rd Int. ICST Conf. NanoNet 2008, Revised Selected Papers, vol. 3, Sep. 2009.

[31] D. Wolpert and P. Ampadu, "Normal and reverse temperature dependence in variation-tolerant nanoscale systems with high-k dielectrics and metal gates," Springer Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering - 3rd Int. ICST Conf. NanoNet 2008, Revised Selected Papers, vol. 3, Sep. 2009.

[32] V. Kaushal, M. Margala, G. Guarino, Q. Yu, W. Donaldson, R. Sobolewski, P. Ampadu, "A study of effects of deflector position variation on leakage currents in ballistic deflection transistors," Proc. IEEE Nanotechnology Materials and Devices Conf. (NMDC'09), pp. 1-6, Jun. 2009.

[33] D. Wolpert, H. Irie, Q. Diduck, M. Margala, R. Sobolewski, P. Ampadu, "Ballistic deflection transistors and the emerging nanoscale era," Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS'09), pp. 61-64, May 2009.

[34] B. Fu, D. Wolpert, P. Ampadu, "Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links," Proc. 3rd ACM/IEEE Int. Symp. on Networks-on-Chip (NoCS'09), pp. 54-64, May 2009.

[35] D. Wolpert and P. Ampadu, "A low-power safety mode for variation tolerant systems-on-chip," Proc. 23rd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Syst. (DFT'08), pp. 1-9, Oct. 2008.

[36] Q. Yu and P. Ampadu, "Adaptive error control for NoC switch-to-switch links in a variable noise environment," Proc. 23rd IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Syst. (DFT'08), pp. 352-360, Oct. 2008.

[37] B. Fu and P. Ampadu, "A multi-wire error correction scheme for reliable and energy efficient SoC links using Hamming product codes," Proc. IEEE Int. SoC Conf. (SoCC'08), pp. 59-62, Sep. 2008.

[38] Q. Yu and P. Ampadu, "Configurable error correction for multi-wire errors in switch-to-switch SoC links," Proc. IEEE Int. SoC Conf. (SoCC'08), pp. 71-74, Sep. 2008.

[39] Q. Yu and P. Ampadu, "Adaptive error control for reliable systems-on-chip," Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS'08), pp. 832-835, May 2008.

[40] D. Huo, Q. Yu, and P. Ampadu, "A ballistic nanoelectronic device simulator," Proc. IEEE/ACM Symp. on Nanoscale Architectures (NANOARCH'07), pp. 38-45, Oct. 2007.

[41] D. Wolpert and P. Ampadu, "Temperature-robust performance yield through supply voltage selection," Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS'07), pp. 2279-2282, May 2007.

[42] B. Fu and P. Ampadu, "Comparative analysis of ultra-low voltage flip-flops for energy efficiency," Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS'07), pp. 1173-1176, May 2007.

[43] Q. Yu and P. Ampadu, "Cell ratio bounds for reliable SRAM operation," Proc. 13th IEEE Int. Conf. on Electronics, Circuits, and Syst. (ICECS'06), pp. 1192-1195, Dec. 2006.

[44] B. Fu and P. Ampadu, "Leakage power minimization of nanoscale CMOS circuits via non-critical path transistor sizing," Proc. Int. Conf. on Electronics, Circuits, and Syst. (ICECS'06), pp. 1101-1104, Dec. 2006.

[45] D. Wolpert and P. Ampadu, "An ultra-low voltage 200 MHz 0.6 pJ add-compare-select unit in 180 nm CMOS," Proc. 49th IEEE Int. Midwest Symp. on Circuits and Syst. (MWSCAS'06), pp. 32-35, Aug. 2006.

[46] B. Fu, Q. Yu, and P. Ampadu, "Energy-delay minimization in nanoscale domino logic," Proc. 16th ACM Great Lakes Symp. on VLSI (GLSVLSI'06), pp. 316-319, Apr. 2006.

[47] B. Fu and P. Ampadu, "Techniques for robust energy efficient subthreshold domino CMOS circuits," Proc. IEEE Int. Symp. on Circuits and Syst. (ISCAS'06), pp. 1247-1250, May 2006.

[48] D. Wolpert and P. Ampadu, "Energy comparison of conventional CMOS and pseudo-NMOS at ultra-low voltages," Proc. 29th Annual IEEE EDS/CAS Act. in Western New York Conf., Nov. 2005.

[49] B. Fu and P. Ampadu, "Ultra-low voltage latches and flip-flops," Proc. 29th Annual IEEE EDS/CAS Act. in Western New York Conf., Nov. 2005.

[50] Q. Yu and P. Ampadu, "Device sizing for leakage reduction in minimum energy circuits," Proc. 29th Annual IEEE EDS/CAS Act. in Western New York Conf., Nov. 2005.

Demonstrations

[51] Q. Yu, M. Zhang, P. Ampadu, "A comprehensive Networks-on-Chip simulator for error control explorations," Proc. 5th ACM/IEEE Int. Symp. on Networks-on-Chip (NoCS'11), pp. 263-264, May 2011.