Publications

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering
Department of Electrical and Computer Engineering
University of Rochester
Rochester, New York 14627
USA

Authored Books
  1. M. El-Moursy and E. Friedman, On-Chip Inductive Interconnect Design Methodologies, VDM Verlag Dr. Muller Aktiengesellschaft & Company, 2009, ISBN 978-3-639-15724-6.

  2. I. S. Kourtev, B. Taskin, and E. G. Friedman, Timing Optimization Through Clock Skew Scheduling, Second Edition, Springer Science+Business Media, 2009, ISBN # 978-0-387-71055-6.

  3. V. F. Pavlidis and E. G. Friedman, Three-Dimensional Integrated Circuit Design, Morgan Kaufmann, 2009, ISBN # 978-0-12-374343-5.

  4. M. Popovich, A. V. Mezhiba, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer Verlag, 2008, ISBN # 978-0-387-71600-8.

  5. V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design, West Sussex, England:John Wiley & Sons Press, 2006, ISBN # 0-470-01023-1. Chinese translation by China Machine Press, 2008, ISBN # 978-7-111-23864-5.

  6. A. V. Mezhiba and E. G. Friedman, Power Distribution Networks in High Speed Integrated Circuits, Norwell, Massachusetts:Kluwer Academic Publishers, 2004, ISBN # 1-4020-7534-0. See Book Review by M. Stojcev.

  7. Y. I. Ismail and E. G. Friedman, On-Chip Inductance in High Speed Integrated Circuits, Norwell, Massachusetts:Kluwer Academic Publishers, 2001, ISBN # 0-7923-7293-X.

  8. I. S. Kourtev and E. G. Friedman, Timing Optimization Through Clock Skew Scheduling, Norwell, Massachusetts:Kluwer Academic Publishers, 2000, ISBN # 0-7923-7796-6.

Edited Books
  1. M. A. Bayoumi and E. G. Friedman (Eds.), Proceedings of the IEEE Workshop on Signal Processing Systems Design and Implementation, IEEE Press, 2000, ISBN # 0-7803-6488-0.

  2. J. J. Becerra and E. G. Friedman (Eds.), Analog Design Issues in Digital VLSI Circuits and Systems, Norwell, Massachusetts:Kluwer Academic Publishers, 1997, ISBN # 0-7923-9950-1.

  3. E. G. Friedman (Ed.), High Performance Clock Distribution Networks, Norwell, Massachusetts:Kluwer Academic Publishers, 1997, ISBN # 0-7923-9967-6.

  4. E. G. Friedman (Ed.), Clock Distribution Networks in VLSI Circuits and Systems, Piscataway, New Jersey:IEEE Press, 1995, ISBN # 0-7803-1058-6.

Book Chapters
  1. I. Savidis and E. G. Friedman, " Physical Design Trends for Interconnects," On-Chip Communication Architectures System on Chip Interconnect, S. Pasricha and N. Dutt, Morgan Kaufmann Publishers, Elsevier, Chapter 11, pp. 403 - 437, 2008, ISBN # 978-0-12-373892-9.

  2. N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Chen, E. G. Friedman, P. M. Fauchet, and D. H. Albonesi, "Alleviating Thermal Constraints while Maintaining Performance via Silicon-Based On-Chip Optical Interconnects," Unique Chips and Systems, E. John and J. Rubio (Eds.), CRC Press, Taylor & Francis Group, LLC, Chapter 14, pp. 339 - 355, 2008, ISBN # 978-1-4200-5174-2.

  3. I. S. Kourtev, B. Taskin, and E. G. Friedman, "System Timing," The VLSI Handbook, Second Edition, W. K. Chen (Ed.), Boca Raton, Florida:CRC Press, Taylor & Francis Group, LLC, Chapter 50, pp. 50-3 - 50-43, 2007, ISBN # 0-8493-4199-X.

  4. I. S. Kourtev and E. G. Friedman, "Clock Skew Scheduling for Improved Reliability," The Electrical Engineering Handbook, W.-K. Chen (Editor-in-Chief), Elsevier Academic Press, Chapter III.4, pp. 231-262, 2005, ISBN # 0-12-170960-4.

  5. M. A. El-Moursy and E. G. Friedman, "Design Methodologies for On-Chip Inductive Interconnect," Interconnect-Centric Design for Advanced SoC and NoC, J. Nurmi, H. Tenhunen, J. Isoaho, and A. Jantsch (Eds.), Norwell, Massachusetts:Kluwer Academic Publishers, Chapter 4, pp. 85-124, 2004, ISBN # 1-4020-7835-8.

  6. M. A. El-Moursy and E. G. Friedman, "Optimizing Inductive Interconnect for Low Power," System-on-Chip for Real-Time Applications, W. Badawy and G. A. Jullien (Eds.), Norwell, Massachusetts:Kluwer Academic Publishers, Section 9.2, pp. 380-391, 2003, ISBN # 1-4020-7254-6.

  7. A. V. Mezhiba and E. G. Friedman, " Trade-offs in CMOS VLSI Circuits," Trade-offs in Analog Circuit Design The Designer's Companion, C. Toumazou, G. Moschytz, and B. Gilbert (Eds.), Dordrecht, The Netherlands:Kluwer Academic Publishers, Chapter 3, pp. 75-114, 2002.

  8. I. S. Kourtev and E. G. Friedman, "System Timing," The VLSI Handbook, W. K. Chen (Ed.), Boca Raton, Florida:IEEE Press/CRC Press LLC, Chapter 47, pp. 47-1 - 47-32, 1999 and Memory, Microprocessors, and ASIC, Boca Raton, Florida:CRC Press, Chapter 1, pp. 1-1 - 1-31, 2003.

  9. E. G. Friedman, "Introduction Clock Distribution Networks in VLSI Circuits and Systems," Clock Distribution Networks in VLSI Circuits and Systems, E. G. Friedman (Ed.), New Jersey:IEEE Press, pp. 1-36, 1995. Also published in High-Performance System Design, V. G. Oklobdzija (Ed.), New Jersey:IEEE Press, pp. 270-305, 1999.

  10. E. G. Friedman and J. H. Mulligan, Jr., "Pipelining and Clocking of High Performance Synchronous Digital Systems," VLSI Signal Processing Technology, M. A. Bayoumi and E. E. Swartzlander, Jr., (Eds.), Norwell, Massachusetts: Kluwer Academic Publishers, Chapter 4, pp. 97-133, 1994.

Refereed Journal Papers
  1. A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny, " Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths with RC Interconnect," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (in press).

  2. G. Chen and E. G. Friedman, " Transient Response of a Distributed RLC Interconnect based on a Direct Pole Extraction," Journal of Circuits, Systems and Computers, Volume 18, Number 7, pp. 1263-1285, November 2009.

  3. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, " Methodology For Efficient Substrate Noise Analysis in Large Scale Mixed-Signal Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, pp. 1405-1418, October 2009.

  4. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, " Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 10, pp. 1559-1564, October 2009.

  5. I. Savidis and E. G. Friedman, " Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance," IEEE Transactions on Electron Devices, Vol. 56, No. 9, pp. 1873-1881, September 2009.

  6. R. Jakushokas and E. G. Friedman, " Inductance Model of Interdigitated Power and Ground Distribution Networks," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 7, pp. 585-589, July 2009.

  7. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, " Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance," IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 56, No. 5, pp. 997-1004, May 2009.

  8. J. Rosenfeld and E. G. Friedman, " Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 2, pp. 181-193, February 2009.

  9. V. F. Pavlidis and E. G. Friedman, " Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits," Proceedings of the IEEE, Vol. 97, No.1, pp. 123-140, January 2009.

  10. M. Popovich, E. G. Friedman, R. Secareanu, and O. L. Hartin, " Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 12, pp. 1717-1721, December 2008.

  11. M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, " On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, pp. 908-921, July 2008.

  12. M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman, " Effective Radii of On-Chip Decoupling Capacitors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, pp. 894-907, July 2008.

  13. V. F. Pavlidis and E. G. Friedman, " Timing Driven Via Placement Heuristics for 3-D ICs," Integration, the VLSI Journal, Volume 41, Issue 4, pp. 489 - 508, July 2008.

  14. G. Chen and E. G. Friedman, " Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis," IEEE Transactions on Circuits and Systems I: Brief Papers, Vol. 55, No. 1, pp. 26-30, January 2008.

  15. V. F. Pavlidis and E. G. Friedman, " 3-D Topologies for Networks-on-Chip," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 10, pp. 1081-1090, October 2007.

  16. M. A. El-Moursy and E. G. Friedman, " Wire Shaping of RLC Interconnects," Integration, the VLSI Journal, Volume 40, Issue 4, pp. 461 - 472, July 2007.

  17. G. Chen, H. Chen, M. Haurylau, N. A. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman, " Predictions of CMOS Compatible On-Chip Optical Interconnect," Integration, the VLSI Journal, Volume 40, Issue 4, pp. 434 - 446, July 2007.

  18. E. Salman, A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman, " Exploiting Setup-Hold Time Interdependency In Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 6, pp. 1114-1125, June 2007.

  19. J. Rosenfeld and E. G. Friedman, " Design Methodology for Global Resonant H-Tree Clock Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 2, pp. 135-148, February 2007.

  20. M. Haurylau, G. Chen, H. Chen, J. Zhang, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, " On-chip Optical Interconnect Roadmap: Challenges and Critical Directions," IEEE Journal of Selected Topics in Quantum Electronics, Vol. 12, No. 6, pp. 1699-1705, November/December 2006.

  21. B. D. Andreev, E. L. Titlebaum, and E. G. Friedman, " Sizing CMOS Inverters with Miller Effect and Threshold Voltage Variations," Journal of Circuits, Systems and Computers, Volume 15, Number 3, pp. 437-454, June 2006.

  22. J. Zhang and E. G. Friedman, " Crosstalk Modeling for Coupled RLC Interconnects with Application to Shield Insertion," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 6, pp. 641-646, June 2006.

  23. M. Popovich and E. G. Friedman, " Decoupling Capacitors for Multi-Voltage Power Distribution Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 3, pp. 217-228, March 2006.

  24. G. Chen and E. G. Friedman, " Low Power Repeaters Driving RC and RLC Interconnects with Delay and Bandwidth Constraints," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 2, pp. 161-172, February 2006.

  25. W. Xu and E. G. Friedman, " On-Chip Test Circuit for Measuring Substrate and Line-to-Line Coupling Noise," IEEE Journal of Solid-State Circuits, Vol. 41, No. 2, pp. 474-482, February 2006.

  26. V. Kursun, V. K. De, E. G. Friedman, and S. G. Narendra, " Monolithic Voltage Conversion in Low-Voltage CMOS Technologies," Microelectronics Journal, Volume 36, Number 9, pp. 863-867, September 2005.

  27. W. Xu and E. G. Friedman, " Clock Feedthrough in CMOS Analog Transmission Gate Switches," Analog Integrated Circuits and Signal Processing, Volume 44, Number 3, pp. 271-281, September 2005.

  28. M. A. El-Moursy and E. G. Friedman, " Exponentially Tapered H-Tree Clock Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 8, pp. 971-975, August 2005.

  29. M. A. El-Moursy and E. G. Friedman, " Shielding Effect of On-Chip Interconnect Inductance," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 3, pp. 396-400, March 2005.

  30. V. Kursun, S.G. Narendra, V.K. De, E.G. Friedman, " Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages," Analog Integrated Circuits and Signal Processing, Volume 42, Number 3, pp. 231-238, March 2005.

  31. G. Chen and E. G. Friedman, " An RLC Interconnect Model Based on Fourier Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 2, pp. 170-183, February 2005.

  32. M. A. El-Moursy and E. G. Friedman, " Power Characteristics of Inductive Interconnect," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 10, pp. 1295-1306, December 2004.

  33. M. A. El-Moursy and E. G. Friedman, " Optimum Wire Sizing of RLC Interconnect With Repeaters," Integration, the VLSI Journal, Volume 38, Issue 2, pp. 205-225, December 2004.

  34. A. V. Mezhiba and E. G. Friedman, " Impedance Characteristics of Power Distribution Grids in Nanoscale Integrated Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 11, pp. 1148-1155, November 2004.

  35. M. A. El-Moursy and E. G. Friedman, " Resistive Power in CMOS Circuits," Analog Integrated Circuits and Signal Processing, Volume 41, Numbers 1, pp. 5-11, October 2004.

  36. B. D. Andreev, E. Titlebaum, and E. G. Friedman, " Complex +/- 1 Multiplier Based on Signed-Binary Transformations," Journal of VLSI Signal Processing, Volume 38, Number 1 pp. 13-24, August 2004.

  37. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, " Low-Voltage-Swing Monolithic dc-dc Conversion," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 51, No. 5, pp. 241-248, May 2004.

  38. V. Kursun and E. G. Friedman, " Sleep Switch Dual Threshold Voltage Domino Logic with Reduced Standby Leakage Current," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp. 485-496, May 2004.

  39. A. V. Mezhiba and E. G. Friedman, " Scaling Trends of On-Chip Power Distribution Noise," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 4, pp. 386-394, April 2004.

  40. R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, I. S. Kourtev, and E. G. Friedman, " Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 1, pp. 67-78, January 2004.

  41. V. Kursun and E. G. Friedman, " Domino Logic with Variable Threshold Keeper," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 6, pp. 1080-1093, December 2003.

  42. D. H. Albonesi, R. Balasubramonian, S. G. Dropsho, S. Dwarkadas, E. G. Friedman, M. C. Huang, V. Kursun, G. Magklis, M. L. Scott, G. Semararo, P. Bose, A. Buyuktosunoglu, P. W. Cook, and S. E. Schuster, "Dynamically Tuning Processor Resources with Adaptive Computing," IEEE Computer, Volume 36, Number 12, pp. 49-58, December 2003.

  43. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, " Analysis of Buck Converters for On-Chip Integration with a Dual Supply Voltage Microprocessor," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 3, pp. 514-522, June 2003.

  44. A. V. Mezhiba and E. G. Friedman, " Frequency Characteristics of High Speed Power Distribution Networks," Analog Integrated Circuits and Signal Processing, Volume 35, Numbers 2/3, pp. 207-214, May/June 2003.

  45. Y. I. Ismail and E. G. Friedman, " On the Extraction of On-Chip Inductance," Journal of Circuits, Systems and Computers, Volume 12, Number 1, pp. 31-40, February 2003.

  46. A. V. Mezhiba and E. G. Friedman, " Inductive Properties of High-Performance Power Distribution Grids," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, pp. 762-776, December 2002.

  47. M. A. El-Moursy and E. G. Friedman, " Optimizing Inductive Interconnect for Low Power," Canadian Journal of Electrical and Computer Engineering, Volume 27, Number 4, pp. 183-187, October 2002.

  48. K. T. Tang and E. G. Friedman, " Simultaneous Switching Noise in On-Chip CMOS Power Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 4, pp. 487-493, August 2002.

  49. Y. I. Ismail and E. G. Friedman, " Inductance Effects in RLC Trees," Journal of Circuits, Systems and Computers, Vol. 11, No. 3, pp. 305-321, June 2002.

  50. D. Velenis, K. T. Tang, I. S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, " Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling," Journal of Circuits, Systems and Computers, Vol. 11, No. 3, pp. 231-245, June 2002.

  51. K. T. Tang and E. G. Friedman, " The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections," Analog Integrated Circuits and Signal Processing, Volume 31, Number 3, pp. 209-224, June 2002.

  52. K. T. Tang and E. G. Friedman, " Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates," Analog Integrated Circuits and Signal Processing, Volume 31, Number 3, pp. 249-259, June 2002.

  53. Y. I. Ismail and E. G. Friedman " DDT: Direct Derivation of Transfer Function. An Alternative to Moment Matching for Tree Structured Interconnect," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, pp. 131-144, February 2002.

  54. X. Liu, M. C. Papaefthymiou, and E. G. Friedman, " Retiming and Clock Scheduling for Digital Circuit Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 2, pp. 184-203, February 2002.

  55. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 963-973, December 2001.

  56. R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits," Analog Integrated Circuits and Signal Processing, Volume 28, Number 3, pp. 253-264, September 2001.

  57. R. M. Secareanu and E. G. Friedman, " Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity," Analog Integrated Circuits and Signal Processing, Volume 27, Number 3, pp. 275-279, June 2001.

  58. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Repeater Insertion in Tree Structured Inductive Interconnect," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 48, No. 5, pp. 471-481, May 2001.

  59. E. G. Friedman, (Invited paper) " Clock Distribution Networks in Synchronous Digital Integrated Circuits," Proceedings of the IEEE, Vol. 89, No. 5, pp. 665-692, May 2001.

  60. V. Adler and E. G. Friedman, " Uniform Repeater Insertion in RC Trees," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 47, No. 10, pp. 1515-1523, October 2000.

  61. K. T. Tang and E. G. Friedman, "Delay and Noise Estimation of CMOS Logic Gates Driving Coupled Resistive-Capacitive Interconnections," Integration, the VLSI Journal, Volume 29, Issue 2, pp. 131-165, September 2000.

  62. Y. I. Ismail and E. G. Friedman, " Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 2, pp. 195-206, April 2000.

  63. Y. I. Ismail, E. G. Friedman, and J. Neves, " Equivalent Elmore Delay for RLC Trees," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 1, pp. 83-97, January 2000.

  64. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Figures of Merit to Characterize the Importance of On-Chip Inductance," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 4, pp. 442-449, December 1999.

  65. I. S. Kourtev and E. G. Friedman, " Synthesis of Clock Tree Topologies to Implement Non-Zero Skew Schedule," IEE Proceedings-Circuits, Devices and Systems, Volume 146, No. 6, pp. 321-326, December 1999.

  66. K. Gaj, Q. P. Herr, V. Adler, D. K. Brock, E. G. Friedman, and M. J. Feldman, " Towards a Systematic Design Methodology for Large Multi-Gigahertz Rapid Single Flux Quantum Circuits," IEEE Transactions on Applied Superconductivity, Vol. 9, No. 13 pp. 4591-4606, September 1999.

  67. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 46, No. 8, pp. 950-961, August 1999.

  68. I. S. Kourtev and E. G. Friedman, " Integrated Circuit Signal Delay," Wiley Encyclopedia of Electrical and Electronics Engineering, J. G. Webster (Ed.), New York, New York: John Wiley & Sons, Inc., Volume 10, pp. 378-392, 1999.

  69. E. G. Friedman, " Clock Distribution in Synchronous Systems," Wiley Encyclopedia of Electrical and Electronics Engineering, J. G. Webster (Ed.), New York, New York: John Wiley & Sons, Inc., Volume 3, pp. 474-497, 1999.

  70. K. Gaj, Q. P. Herr, V. Adler, A. Krasniewski, E. G. Friedman, and M. J. Feldman, " Tools for the Computer-Aided Design of Multi-Gigahertz Superconducting Digital Circuits," IEEE Transactions on Applied Superconductivity, Vol. 9, No. 1, pp. 18-38, March 1999.

  71. V. Adler and E. G. Friedman, "Repeater Design to Reduce Delay and Power in Resistive Interconnect," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. CAS II-45, No. 5, pp. 607-616, May 1998.

  72. J. L. Neves and E. G. Friedman, " Automated Synthesis of Skew-Based Clock Distribution Networks," VLSI Design An International Journal of Custom-Chip Design, Simulation, and Testing, Vol. 7, No.1, pp. 31-57, 1998.

  73. E. G. Friedman and J. H. Mulligan, Jr., " Ramp Input Response of RC Tree Network," Analog Integrated Circuits and Signal Processing, Volume 14, No. 1/2, pp. 53-58, September 1997.

  74. V. Adler and E. G. Friedman, "Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load," Analog Integrated Circuits and Signal Processing, Volume 14, No. 1/2, pp. 29-39, September 1997.

  75. B. S. Cherkauer and E. G. Friedman, "A Hybrid Radix-4/Radix-8 Low Power Signed Multiplier Architecture," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. CAS II-44, No. 8, pp. 656-659, August 1997.

  76. J. L. Neves and E.G. Friedman, " Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations," Journal of VLSI Signal Processing, Volume 16, Numbers 2/3, pp. 149-161, June/July 1997.

  77. K. Gaj, E. G. Friedman, and M. J. Feldman,"Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits," Journal of VLSI Signal Processing, Volume 16, Numbers 2/3, pp. 247-276, June/July 1997.

  78. M. D. Hahm, E. G. Friedman, and E. L. Titlebaum, "A Comparison of Analog and Digital Circuit Implementations of Low-Power Matched Filters for Use in Portable Wireless Communication Terminals," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. CAS II-44, No. 6, pp. 498-506, June 1997.

  79. K. Gaj, C.H. Cheah, E. G. Friedman, and M. J. Feldman, "Functional Modeling of RSFQ Circuits Using Verilog HDL," IEEE Transactions on Applied Superconductivity, Vol. AS-7, No. 2, pp. 3151-3154, June 1997.

  80. Q. P. Herr, N. Vukovic, C. A. Mancini, K. Gaj, Q. Ke, V. Adler, E. G. Friedman, A. Krasniewski, M. F. Bocko, and M. J. Feldman, "Design and Low Speed Testing of a Four-Bit RSFQ Multiplier-Accumulator," IEEE Transactions on Applied Superconductivity, Vol. AS-7, No. 2, pp. 3168-3171, June 1997.

  81. V. Adler, C.-H. Cheah, K. Gaj, D. K. Brock, and E. G. Friedman, "A Cadence-Based Design Environment for Single Flux Quantum Circuits," IEEE Transactions on Applied Superconductivity, Vol. AS-7, No. 2, pp. 3294-3297, June 1997.

  82. T. Soyata, E. G. Friedman, and J. H. Mulligan, Jr., "Incorporating Interconnect, Register, and Clock Distribution Delays into the Retiming Process," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-16, No. 1, pp. 105-120, January 1997.

  83. J. L. Neves and E. G. Friedman," Design Methodology for Synthesizing Clock Distribution Networks Exploiting Non-Zero Clock Skew," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. VLSI-4, No. 2, pp. 286-291, June 1996.

  84. K. Gaj, E.G. Friedman, M.J. Feldman, and A. Krasniewski, "A Clock Distribution Scheme for Large RSFQ Circuits," IEEE Transactions on Applied Superconductivity, Vol. AS-5, No.2, pp. 3320-3324, June 1995.

  85. B. S. Cherkauer and E. G. Friedman," A Unified Design Methodology for CMOS Tapered Buffers," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. VLSI-3, No. 1, pp. 99-111, March 1995.

  86. B. S. Cherkauer and E. G. Friedman, "Design of Tapered Buffers with Local Interconnect Capacitance," IEEE Journal of Solid-State Circuits, Vol. SC-30, No. 2, pp. 151-155, February 1995.

  87. B. S. Cherkauer and E. G. Friedman, " Channel Width Tapering of Serially Connected MOSFETs with Emphasis on Power Dissipation,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. VLSI-2, No. 1, pp. 100-114, March 1994.

  88. E. G. Friedman, " Latching Characteristics of a CMOS Bistable Register," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. CAS-40, No. 12, pp. 902-908, December 1993.

  89. E. G. Friedman, " The Limiting Performance of a CMOS Bistable Register Based on Waveform Considerations," International Journal of Electronics, Volume 73, No. 2, pp. 371-384, August 1992.

  90. E. G. Friedman and J. H. Mulligan, Jr., " Pipelining of High Performance Synchronous Digital Systems," International Journal of Electronics, Volume 70, No. 5, pp. 917-935, May 1991.

  91. E. G. Friedman and J. H. Mulligan, Jr., " Clock Frequency and Latency in Synchronous Digital Systems,," IEEE Transactions on Signal Processing, Vol. SP-39, No. 4, pp. 930-934, April 1991.

  92. G. Yacoub, H. Pham, M. Ma, and E. G. Friedman, " A System for Critical Path Analysis Based on Back Annotation and Distributed Interconnect Impedance Models," Microelectronics Journal, Vol. 19, No. 3, pp. 21-30, May/June 1988.

  93. E. G. Friedman and S. Powell, " Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macrocell VLSI," IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 2, pp. 240-246, April 1986.

  94. E. G. Friedman, G. Yacoub, and S. Powell, " A CMOS/SOS VLSI Design System," Journal of Semi-Custom ICs, Vol. 2, No. 4, pp. 5-11, June 1985.

  95. E. G. Friedman, " Feedback in Silicon Compilers," IEEE Circuits and Devices, Vol. 1, No. 3, pp. 15-20, May 1985.

  96. S. Powell, E. Iodice, and E. Friedman, " An Automated, Low Power, High Speed Complementary PLA Design System for VLSI Applications," Microelectronics Journal, Vol. 15, No. 4, pp. 47-54, July/August 1984.

  97. E. Friedman and G. Yacoub, " A Two Level Metal, Software Compatible, CMOS/SOS Gate Array Family," Microelectronics Journal, Vol. 14, No. 6, pp. 117-118, November/December 1983.

Refereed Conference Papers
  1. J. Xue, A. Garg, B. Ciftcioglu, S. Wang, I. Savidis, J. Hu, M. Jain, M. Huang, H. Wu, E. G. Friedman, G. W. Wicks, and D. Moore, " An Intra-Chip Free-Space Optical Interconnect," Proceedings of the 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI) in conjunction with the International Symposium on Computer Architecture, June 2009.

  2. R. Jakushokas and E. G. Friedman, " Minimizing Noise via Shield and Repeater Insertion," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2265 - 2268, May 2009.

  3. S. Kose, E. Salman, and E. G. Friedman, " Shielding Methodologies in the Presence of Power/Ground Noise," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2277 - 2280, May 2009.

  4. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O L. Hartin, " Contact Merging Algorithm for Efficient Substrate Noise Analysis in Large Scale Circuits," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 9 -14, May 2009.

  5. I. Vaisband, R. Ginosar, A. Kolodny, and E. G. Friedman, " Power Efficient Tree-Based Crosslinks for Skew Reduction," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 285 - 290, May 2009.

  6. R. Jakushokas and E. G. Friedman, " Simultaneous Shield and Repeater Insertion," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 15 - 19, May 2009.

  7. I. Savidis, E. G. Friedman, V. F. Pavlidis, and G. De Micheli, " Clock and Power Distribution Networks for 3-D Integrated Circuits," Proceedings of the Workshop on 3D Integration, Design, Automation & Test in Europe Conference, March 2009.

  8. J. Rosenfeld and E. G. Friedman, " On-Chip DC-DC Converters for Three-Dimensional ICs," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 759 - 764, March 2009.

  9. V. F. Pavlidis, I. Savidis, and E. G. Friedman, " Clock Distribution Architectures for 3-D SOI Integrated Circuits," Proceedings of the IEEE International SOI Conference, pp. 111-112, October 2008.

  10. D. Velenis, M. C. Papaefthymiou and E. G. Friedman, " Physical Design for Reduced Delay Uncertainty in High Performance Clock Distribution Networks," Proceedings of the IFIP/IEEE VLSI - SOC Conference, pp. 531-534, October 2008.

  11. V. F. Pavlidis, I. Savidis, and E. G. Friedman, " Clock Distribution Networks for 3-D Integrated Circuits," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 651-654, September 2008.

  12. A. Lavzin, M. Kozak, and E. G. Friedman, " A Higher-Order Mismatch-Shaping Method for Multi-Bit Sigma-Delta Modulators," Proceedings of the IEEE International SoC Conference, pp. 267-270, September 2008.

  13. M. Popovich and E. G. Friedman, " Nanoscale On-Chip Decoupling Capacitors," Proceedings of the IEEE International SoC Conference, pp. 51-54, September 2008.

  14. S. Kose, E. Salman, Z. Ignjatovic, and E. G. Friedman, " Pseudo-Random Clocking to Enhance Signal Integrity," Proceedings of the IEEE International SoC Conference, pp. 47-50, September 2008.

  15. E. Salman and E. G. Friedman, " Methodology for Placing Localized Guard Rings to Reduce Substrate Noise in Mixed-Signal Circuits," Proceedings of the Fourth Conference on PhD Research on Microelectronics and Electronics (PRIME 08), pp. 85-88, June 2008.

  16. G. Chen and E. G. Friedman, " Transient Simulation of On-Chip Transmission Lines via Exact Pole Extraction," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2757 - 2760, May 2008.

  17. E. Salman, E. G. Friedman, R. M. Secareanu, and O L. Hartin, " Equivalent Rise Time for Resonance in Power/Ground Noise Estimation," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2422 - 2425, May 2008.

  18. I. Savidis and E. G. Friedman, " Electrical Characterization and Modeling of 3-D Vias," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 784 - 787, May 2008.

  19. E. Salman, R. Jakushokas, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, " Input Port Reduction for Efficient Substrate Extraction in Large Scale IC's," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 376 - 379, May 2008.

  20. A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny, " Timing Optimization in Logic with Interconnect," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 19 - 26, April 2008.

  21. E. Salman, E. G. Friedman, R. M. Secareanu, and O L. Hartin, " Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 261 - 266, March 2008.

  22. M. Popovich, E. G. Friedman, R. Secareanu, and O. L. Hartin, " Efficient Placement of Distributed On-Chip Decoupling Capacitors in Nanoscale ICs," Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 811 - 816, November 2007.

  23. G. Chen, H. Chen, M. Haurylau, N. A. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman, " On-Chip Optical Interconnects: Challenges and Critical Directions," Proceedings of the European Optical Society Topical Meeting on Optical Microsystems, p. 97, October 2007.

  24. G. Chen, H. Chen, M. Haurylau, N. Nelson, D. Albonesi, P. Fauchet, and E. G. Friedman, " On-Chip Optical Interconnect for Reduced Delay Uncertainty," Proceedings of Nano-Net, September 2007.

  25. J. Rosenfeld and E. G. Friedman, " Quasi-Resonant Interconnects: A Low Power Design Methodology," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 641 - 644, May 2007.

  26. E. Salman, E. G. Friedman, R. M. Secareanu, and O. L. Hartin, " Substrate Noise Reduction Based on Noise Aware Cell Design," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3227 - 3230, May 2007.

  27. J. Rosenfeld and E. G. Friedman, " Low Power Quasi-Resonant Interconnects," Proceedings of the 30th Annual IEEE EDS/CAS Activities in Western New York Conference, November 2006.

  28. J. Zhang, M. Haurylau, H. Chen, G. Chen, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, " A Semi-Analytical Simulation Model for Capacitor Based E-O Modulators," Proceedings of the 90th OSA Annual Meeting, Frontiers in Optics, paper FWO2, October 2006.

  29. E. Salman, E. G. Friedman, and R. M. Secareanu, " Substrate and Ground Noise Interactions in Mixed-Signal Circuits," Proceedings of the IEEE International SOC Conference, pp. 293-296, September 2006.

  30. V. F. Pavlidis and E. G. Friedman, " 3-D Topologies for Networks-on-Chip," Proceedings of the IEEE International SOC Conference, pp. 285-288, September 2006.

  31. G. Chen, H. Chen, M. Haurylau, N. A. Nelson, D. H. Albonesi, P. M. Fauchet, and E. G. Friedman, " On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions," Proceedings of the IEEE International Interconnect Technology Conference, pp. 39-41, June 2006.

  32. V. Pavlidis and E. G. Friedman, " Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4587-4590, May 2006.

  33. J. Rosenfeld and E. G. Friedman, " Design Methodology for Global Resonant H-Tree Clock Distribution Networks," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2073-2076, May 2006.

  34. G. Chen and E. G. Friedman, " Effective Capacitance of RLC Loads for Estimating Short-Circuit Power," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2065-2068, May 2006.

  35. M. Sotman, A. Kolodny, M. Popovich, and E. G. Friedman, " On-Die Decoupling Capacitance: Frequency Domain Analysis of Activity Radius," Proceedings of the IEEE International Symposium on Circuits and Systems, 489-492, May 2006.

  36. M. A. El-Moursy and E. G. Friedman, " Optimum Wire Tapering for Minimum Power Dissipation in RLC Interconnects," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 485-488, May 2006.

  37. M. Popovich, E. G. Friedman, M. Sotman, A. Kolodny, and R. M. Secareanu " Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 173-179, April/May 2006.

  38. J. Rosenfeld and E. G. Friedman, " Sensitivity Evaluation of Global Resonant H-Tree Clock Distribution Networks," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 192-197, April/May 2006.

  39. E. Salman, A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman, " Pessimism Reduction in Static Timing Analysis Using Interdependent Setup and Hold Times," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 159-164, March 2006.

  40. M. Sotman, M. Popovich, A. Kolodny, and E. Friedman, " "Leveraging Symbiotic On-Die Decoupling Capacitance," Proceedings of the IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 111-114, October 2005.

  41. M. Haurylau, H. Chen, J. Zhang, G. Chen, N. A. Nelson, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, " On-chip Optical Interconnect Roadmap: Challenges and Critical Directions," Proceedings of the IEEE International Conference on Group IV Photonics, pp. 17-19, September 2005.

  42. M. Popovich, E. G. Friedman, R. Secareanu, and O. L. Hartin, " "On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits," Proceedings of the IEEE International SOC Conference, pp. 309-312, September 2005.

  43. V. Kursun, G. Schrom, V. K. De, E. G. Friedman, and S. G. Narendra, " Cascode Buffer for Monolithic Voltage Conversion Operating at High Input Supply Voltages," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 464-467, May 2005.

  44. G. Chen and E. G. Friedman, " A Fourier Series-Based RLC Interconnect Model for Periodic Signals," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4126-4129, May 2005.

  45. G. Chen, H. Chen, M. Haurylau, N. Nelson, D. Albonesi, P. M. Fauchet, and E. G. Friedman, " Electrical and Optical On-Chip Interconnects in Scaled Microprocessors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2514-2517, May 2005.

  46. G. Chen and E. G. Friedman, " Low Power Repeater Driving RLC Interconnect with Delay and Bandwidth Constraints," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 596-599, May 2005.

  47. M. Popovich and E. G. Friedman, " Noise Coupling in Multi-Voltage Power Distribution Systems with Decoupling Capacitors," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 620-623, May 2005.

  48. R. M. Secareanu, S. K. Banerjee, O. Hartin, V. Fernandez, and E. G. Friedman, " Managing Substrate and Interconnect Noise from High Performance Repeater Insertion in a Mixed-Signal Environment," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 612-615, May 2005.

  49. V. Pavlidis and E. G. Friedman, " Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs," Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 20-25, April 2005.

  50. M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, " On-Chip Power Distribution Grids with Multiple Supply Voltages for High Performance Integrated Circuits," Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 2-7, April 2005 (received best student paper award for GLSVLSI 2005).

  51. G. Chen, H. Chen, M. Haurylau, N. Nelson, D. Albonesi, P. M. Fauchet, and E. G. Friedman, " Predictions of CMOS Compatible On-Chip Optical Interconnect," Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 13-20, April 2005.

  52. M. Popovich and E. G. Friedman, " Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems," Proceedings of the IEEE International Sympoisum of Quality Electronic Design, pp. 334-339, March 2005.

  53. N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Chen, D. H. Albonesi, E. G. Friedman, and P. M. Fauchet, " Alleviating Thermal Constraints While Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects," Proceedings of the Workshop on Unique Chips and Systems (UCAS-1), pp. 45-52, March 2005.

  54. J. Rosenfeld, M. Kozak, and E. G. Friedman, " A Bulk-Driven CMOS OTA with 68 dB DC Gain," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 5-8, December 2004.

  55. B. Shem-Tov, M. Kozak, and E. G. Friedman, " A 250 MHz Delta-Sigma Modulator for Low Cost Ultrasound/Sonar Beamforming Applications," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 113-116, December 2004.

  56. M. Popovich and E. G. Friedman, " Impedance Characteristics of Decoupling Capacitors in Multi-Power Distribution Systems," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 160-163, December 2004.

  57. E. G. Friedman, " Challenges in Ultra Submicrometer High Performance VLSI Circuits," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, p. 238, December 2004.

  58. D. Velenis, R. Sundaresha, and E. G. Friedman, " Buffer Sizing for Delay Uncertainty Induced by Process Variations," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 415-418, December 2004.

  59. B. Shem-Tov, M. Kozak, and E. G. Friedman, " A High-Speed CMOS Op-Amp Design Technique using Negative Miller Capacitance," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 623-626, December 2004.

  60. M. Popovich and E. G. Friedman, " Decoupling Capacitors for Power Distribution Systems with Multiple Power Supplies," Proceedings of the 28th Annual IEEE EDS/CAS Activities in Western New York Conference, p. 9, November 2004.

  61. D. Velenis and E. G. Friedman, " Buffer Sizing for Crosstalk Induced Delay Uncertainty," Proceedings of the International Workshop on Power and Timing Modeling, Optimization, and Simulation, pp. 750-759, September 2004.

  62. M. Popovich and E. G. Friedman, " Decoupling Capacitors for Power Distribution Systems with Multiple Power Supply Voltages," Proceedings of the IEEE International SOC Conference, pp. 331-334, September 2004.

  63. G. Chen and E. G. Friedman, " Low Power Repeaters Driving RC Interconnect with Delay and Bandwidth Constraints," Proceedings of the IEEE International SOC Conference, pp. 335-339, September 2004.

  64. J. Zhang and E. G. Friedman, " Mutual Inductance Modeling for Multiple RLC Interconnects with Application to Shield Insertion," Proceedings of the IEEE International SOC Conference, pp. 344-347, September 2004.

  65. D. Velenis, M. C. Papaefthymiou, and E. G. Friedman, " Clock Tree Layout Design for Reduced Delay Uncertainty," Proceedings of the IEEE International SOC Conference, pp. 179-180, September 2004.

  66. B. D. Andreev, E. L. Titlebaum, and E. G. Friedman, " Low Power Flexible Rake Receivers for WCDMA," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 97-100, May 2004.

  67. M. A. El-Moursy and E. G. Friedman, " Exponentially Tapered H-Tree Clock Distribution Networks," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. II, pp. 601-604, May 2004.

  68. V. Kursun and E. G. Friedman, " Energy Efficient Dual Threshold Voltage Dynamic Circuits Employing Sleep Switches to Minimize Subthreshold Leakage," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. II, pp. 417-420, May 2004.

  69. V. Kursun and E. G. Friedman, " Forward Body Biased Keeper for Enhanced Noise Immunity in Domino Logic Circuits," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. II, pp. 917-920, May 2004.

  70. J. Zhang and E. G. Friedman, " Effect of Shield Insertion on Reducing Crosstalk Noise Between Coupled Interconnects," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. II, pp. 529-532, May 2004.

  71. J. Zhang and E. G. Friedman, " Decoupling Technique and Crosstalk Analysis of Coupled RLC Interconnects," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. II, pp. 521-524, May 2004.

  72. M. Kozak and E G. Friedman, " Design and Simulation of Fractional-N PLL Frequency Synthesizers," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 780-783, May 2004.

  73. J. Zhang, S. R. Cooper, A. R. LaPietra, M. W. Mattern, R. M. Guidash, and E. G. Friedman, " A Low Power Thyristor-Based CMOS Programmable Delay Element," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. I, pp. 769-772, May 2004.

  74. S. Bhansali, G. H. Chapman, E. Friedman, Y. Ismail, P. R. Mukund, D. Tebbe, and V. Jain, " 3-D Heterogeneous Sensor System on a Chip for Defense and Security Applications," Proceedings of the SPIE Security and Defense Symposium, Volume 5417, pp. 413-424, April 2004.

  75. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, " High Input Voltage Step-Down DC-DC Converters For Integration in a Low Voltage CMOS Process," Proceedings of the IEEE International Symposium on Quality Electronics Design, pp. 517-521, March 2004.

  76. V. Kursun and E. G. Friedman, " Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits," Proceedings of the IEEE International Symposium on Quality Electronics Design, pp. 104-109, March 2004.

  77. M. A. El-Moursy and E. G. Friedman, " Resistive Power in CMOS Circuits," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, December 2003.

  78. M. A. El-Moursy and E. G. Friedman, " Optimum Wire Shaping of an RLC Interconnect," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, December 2003.

  79. M. A. El-Moursy and E. G. Friedman, " Power Characteristics of Inductive Interconnect," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, Vol. II, pp. 499-502, December 2003.

  80. J. Zhang and E. G. Friedman, " Crosstalk Noise Model for Shielded Interconnects in VLSI-based Circuits," Proceedings of the IEEE International SOC Conference, pp. 243-244, September 2003.

  81. J. Rosenfeld, M. Kozak, and E. G. Friedman, " A 0.8 Volt High Performance OTA Using Bulk-Driven MOSFETs for Low Power Mixed-Signal SOCs," Proceedings of the IEEE International SOC Conference, pp. 245-246, September 2003.

  82. V. Kursun and E. G. Friedman, " Speed and Noise Immunity Enhanced Low Power Dynamic Circuits," Proceedings of the Semiconductor Research Corporation Techcon 2003 Conference, August 2003.

  83. B. D. Andreev, E. L. Titlebaum, and E. G. Friedman, " Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic," Proceedings of the IEEE International Workshop on System-on-Chip for Real-Time Applications, pp. 70-75, July 2003.

  84. M. A. El-Moursy and E. G. Friedman, " Inductive Interconnect Width Optimization for Low Power," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 5.273-5.276, May 2003.

  85. A. V. Mezhiba and E. G. Friedman, " Electrical Characteristics of Multi-Layer Power Distribution Grids," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 5.473-5.476, May 2003.

  86. B. D. Andreev, E. L. Titlebaum, and E. G. Friedman, " Orthogonal Code Generator for 3G Wireless Transceivers," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 229-232, April 2003.

  87. M. A. El-Moursy and E. G. Friedman, " Shielding Effect of On-Chip Interconnect Inductance," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 165-170, April 2003.

  88. M. A. El-Moursy and E. G. Friedman, " Optimum Wire Sizing of RLC Interconnect With Repeaters," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 27-32, April 2003.

  89. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, " Monolithic DC-DC Converter Analysis and MOSFET Gate Voltage Optimization," Proceedings of the IEEE International Symposium on Quality Electronics Design, pp. 279-284, March 2003.

  90. D. Velenis, M. C. Papaefthymiou and E. G. Friedman, " Reduced Delay Uncertainty in High Performance Clock Distribution Networks," Proceedings of the Design Automation and Test in Europe (DATE) Conference, pp. 68-73, March 2003.

  91. S. Dropsho, V. Kursun, D. H. Albonesi, S. Dwarkadas, and E. G. Friedman, " Managing Static Leakage Energy in Microprocessor Functional Units," Proceedings of the IEEE/ACM International Symposium on Microarchitecture, pp. 321-332, November 2002.

  92. M. A. El-Moursy and E. G. Friedman, " Optimum Wire Sizing and Repeater Insertion in Distributed RLC Interconnect, Proceedings of the 26th Annual IEEE EDS/CAS Activities in Western New York Conference, p. 6, November 2002.

  93. V. Kursun, S. G. Narendra, V. K. De, and E. G. Friedman, " Efficiency Analysis of a High Frequency Buck Converter for On-Chip Integration with a Dual-VDD Microprocessor," Proceedings of the European Solid-State Circuit Conference, pp. 743-746, September 2002.

  94. V. Kursun and E G. Friedman, " Domino Logic with Dynamic Body Biased Keeper," Proceedings of the European Solid-State Circuit Conference, pp. 675-678, September 2002.

  95. W. Xu and E. G. Friedman, " A CMOS Miller Hold Capacitance Sample-and-Hold Circuit To Reduce Charge Sharing Effect and Clock Feedthrough," Proceedings of the IEEE International ASIC/SOC Conference, pp. 92-96, September 2002.

  96. W. Xu and E. G. Friedman, " Clock Feedthrough in CMOS Analog Transmission Gate Switches," Proceedings of the IEEE International ASIC/SOC Conference, pp. 181-185, September 2002.

  97. W. Xu and E. G. Friedman, " A Circuit Technique for Accurately Measuring Coupling Capacitance," Proceedings of the IEEE International ASIC/SOC Conference, pp. 176-180, September 2002.

  98. V. Kursun and E. G. Friedman, " Variable Threshold Voltage Keeper for Contention Reduction in Dynamic Circuits," Proceedings of the IEEE International ASIC/SOC Conference, pp. 314-318, September 2002.

  99. A. V. Mezhiba and E. G. Friedman, " Variation of Inductance with Frequency in High Performance Power Distribution Grids," Proceedings of the IEEE International ASIC/SOC Conference, pp. 421-425, September 2002.

  100. B. D. Andreev, E. Titlebaum, and E. G. Friedman, " Tapered Transmission Gate Chains for Improved Carry Propagation," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, Vol. III, pp. 449-452, August 2002.

  101. M. A. El-Moursy and E. G. Friedman, " Optimizing Inductive Interconnect for Low Power," Proceedings of the International Workshop on System-on-Chip for Real-Time Applications, pp. 206-216, July 2002.

  102. V. Kursun, R. M. Secareanu, and E. G. Friedman, " CMOS Voltage Interface Circuit for Low Power Systems," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3.667-3.670, May 2002.

  103. R. Mader, E. G. Friedman, A. Litman, and I. S. Kourtev, " Large Scale Clock Skew Scheduling Techniques for Improved Reliability of Digital Synchronous VLSI Circuits," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.357-1.360, May 2002.

  104. W. Xu and E. G. Friedman, " A Substrate Noise Circuit for Accurately Testing Mixed-Signal ICs," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.145-1.148, May 2002.

  105. A. V. Mezhiba and E. G. Friedman, " Inductance/Area/Resistance Tradeoffs in High Performance Power Distribution Grids," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.101-1.104, May 2002.

  106. B. D. Andreev, E. G. Friedman, and E. L. Titlebaum, " Efficient Implementation of a Complex +/- 1 Multiplier," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 83-88, April 2002.

  107. V. Kursun and E. G. Friedman, " Low Swing Dual Threshold Voltage Domino Logic," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 47-52, April 2002.

  108. A. V. Mezhiba and E. G. Friedman, " Properties of On-Chip Inductive Current Loops," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 12-17, April 2002.

  109. A. V. Mezhiba and E. G. Friedman, " Scaling Trends of On-Chip Power Distribution Noise," Proceedings of the IEEE International Workshop on System-Level Interconnect Prediction Conference, pp. 47-53, April 2002.

  110. A. V. Mezhiba and E. G. Friedman, " Inductive Properties of Power Distribution Grids in High Speed Integrated Circuits," Proceedings of the IEEE International Symposium on Quality Electronics Design, pp. 316-321, March 2002.

  111. V. Kursun, R. M. Secareanu, and E. G. Friedman, " Low Power CMOS Bi-Directional Voltage Converter," Proceedings of the 25rd Annual IEEE EDS/CAS Activities in Western New York Conference, pp. 6-7, November 2001.

  112. D. Velenis, K. T. Tang, I. S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, " Demonstration of Power Enhancements on an Industrial Circuit Through Delay Management of Non-Critical Data Paths," Proceedings of the IEEE ASIC Conference, pp. 30-33, September 2001.

  113. R. M. Secareanu, D. Albonesi, and E. G. Friedman, " A Dynamic Reconfigurable Clock Generator," Proceedings of the IEEE ASIC Conference, pp. 330-333, September 2001.

  114. R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " A Comparative Study of the Behavior of NMOS and CMOS Digital Circuits under Substrate Noise," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 181-184, September 2001.

  115. D. Velenis, K. T. Tang, I. S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, " Demonstration of Speed Enhancements in an Industrial Circuit Through Application of Non-Zero Clock Skew Scheduling," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 1021-1025, September 2001.

  116. K. T. Tang and E. G. Friedman, " Estimation of Transient Voltage Fluctuations in the CMOS-Based Power Distribution Networks," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 5.463-5.466, May 2001.

  117. D. Velenis, E. G. Friedman, and M. C. Papaefthymiou, " A Clock Tree Topology Extraction Algorithm for Improving the Tolerance of Clock Distribution Networks to Delay Uncertainty," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4.422-4.425, May 2001.

  118. D. Velenis, K. T. Tang, I. S. Kourtev, V. Adler, F. Baez, and E. G. Friedman, " Demonstration of Speed and Power Enhancements through Application of Non-Zero Clock Skew Scheduling," Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 58-63, December 2000.

  119. K. T. Tang and E. G. Friedman, " Delay Uncertainty Due to On-Chip Simultaneous Switching Noise in High Performance CMOS Integrated Circuits," Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 633-642, October 2000.

  120. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 643-652, October 2000.

  121. K. T. Tang and E. G. Friedman, " Estimation of On-Chip Simultaneous Switching Noise on Signal Delay in Synchronous CMOS Integrated Circuits," Proceedings of the Semiconductor Research Corporation Techcon 2000 Conference, p. 173, September 2000.

  122. K. T. Tang and E. G. Friedman, " On-Chip Delta I Noise in the Power Distribution Networks of High Speed CMOS Integrated Circuits," Proceedings of the IEEE ASIC Conference, pp. 53-57, September 2000.

  123. R. M. Secareanu and E. G. Friedman, " A Differential High-Speed Digital CMOS Buffer with Hysteresis for Improved Noise Immunity," Proceedings of the IEEE ASIC Conference, pp. 326-329, September 2000.

  124. Y. I. Ismail and E. G. Friedman, " Fast and Accurate Simulation of Tree Structured Interconnect," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 1130-1134, August 2000.

  125. Y. I. Ismail and E. G. Friedman, " Exploiting On-Chip Inductance in High Speed Clock Distribution Networks," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 1236-1239, August 2000.

  126. R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " Placement of Substrate Contacts to Alleviate Substrate Noise in Epi and Non-Epi Technologies," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 1314-1318, August 2000.

  127. R. M. Secareanu and E. G. Friedman, " Low Power Digital CMOS Buffer Systems for Driving Highly Capacitive Interconnect Lines," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 362-365, August 2000.

  128. K. T. Tang and E. G. Friedman, " Transient IR Voltage Drops in CMOS-Based Power Distribution Networks," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 1396-1399, August 2000.

  129. K. T. Tang and E. G. Friedman, " Lumped Versus Distributed RC and RLC Interconnect Impedances," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 136-139, August 2000.

  130. R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " Physical Design to Improve the Noise Immunity of Digital Circuits in a Mixed-Signal Smart-Power System," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4.277-4.280, May 2000.

  131. K. T. Tang and E. G. Friedman, " Transient Analysis of a CMOS Inverter Driving Resistive Interconnect," Proceedings of the IEEE International Symposium on Circuits and Systems, 4.269-4.272, May 2000.

  132. Y. I. Ismail and E. G. Friedman " Sensitivity of Interconnect Delay to On-Chip Inductance," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3.403-3.406, May 2000.

  133. K. T. Tang and E. G. Friedman, " Delay and Power Expressions Characterizing a CMOS Inverter Driving an RLC Load," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3.283-3.286, May 2000.

  134. K. T. Tang and E. G. Friedman, " Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits," Proceedings of the International Conference on Modeling and Simulation of Microsystems, pp. 313-316, March 2000.

  135. K. T. Tang and E. G. Friedman, " Noise Estimation Due to Signal Activity for Capacitively Coupled CMOS Logic Gates," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 171-176, March 2000.

  136. R. M. Secareanu and E. G. Friedman, " Transparent Repeaters," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 63-66, March 2000.

  137. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Repeater Insertion in Tree Structured Inductive Interconnect," Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 420-424, November 1999.

  138. I. S. Kourtev and E. G. Friedman, " "Clock Skew Scheduling for Improved Reliability via Quadratic Programming," Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 239-243, November 1999.

  139. R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " Substrate Contact Placement for Substrate Noise Immunity in Epi and Non-Epi Technologies," Proceedings of the 23rd Annual IEEE EDS/CAS Activities in Western New York Conference, pp. 10-11, November 1999.

  140. E. G. Friedman, " The Next Bottleneck in High Speed VLSI: Interconnect Noise," Proceedings of the 23rd Annual IEEE EDS/CAS Activities in Western New York Conference, pp. 3-4, November 1999.

  141. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Optimizing RLC Tree Delays by Employing Repeater Insertion," Proceedings of the IEEE International ASIC/SOC Conference, pp. 14-18, September 1999.

  142. I. S. Kourtev and E. G. Friedman, " A Quadratic Programming Approach to Clock Skew Scheduling for Reduced Sensitivity to Process Parameter Variations," Proceedings of the IEEE International ASIC/SOC Conference, pp. 210-215, September 1999.

  143. K. T. Tang and E. G. Friedman, "Peak Crosstalk Noise Estimation in CMOS VLSI Circuits," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 1539-1542, September 1999.

  144. R. M. Secareanu, V. Adler, and E. G. Friedman, "Exploiting Hysteresis in a CMOS Buffer," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 205-208, September 1999.

  145. X. Liu, M. C. Papaefthymiou, and E. G. Friedman, " Maximizing Performance by Retiming and Clock Skew Scheduling," Proceedings of the IEEE/ACM Design Automation Conference, pp. 231-236, June 1999.

  146. Y. I. Ismail and E. G. Friedman, " Equivalent Elmore Delay for RLC Trees," Proceedings of the IEEE/ACM Design Automation Conference, pp. 715-720, June 1999.

  147. Y. I. Ismail and E. G. Friedman, " Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits," Proceedings of the IEEE/ACM Design Automation Conference, pp. 721-724, June 1999.

  148. R. M. Secareanu and E. G. Friedman, " A Universal CMOS Voltage Interface Circuit," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.242-1.245, May 1999.

  149. K. T. Tang and E. G. Friedman, " Peak Noise Prediction in Loosely Coupled Interconnect," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1.541-1.544, May 1999.

  150. R. M. Secareanu and E. G. Friedman, " A High Precision CMOS Current Mirror/Divider," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2.314-2.317, May 1999.

  151. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Signal Waveform Characterization in RLC Trees," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 6.190-6.193, May 1999.

  152. Y. I. Ismail and E. G. Friedman, " Repeater Insertion in RLC Lines for Minimum Propagation Delay," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 6.404-6.407, May 1999.

  153. R. M. Secareanu, I. S. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " The Behavior of Digital Circuits under Substrate Noise in a Mixed-Signal Smart Power Environment," Proceedings of the IEEE International Symposium on Power Semiconductor Devices and ICs, pp. 253-256, May 1999.

  154. K. T. Tang and E. G. Friedman," Interconnect Coupling Noise in CMOS VLSI Circuits," Proceedings of the ACM International Symposium on Physical Design, pp. 48-53, April 1999.

  155. E. G. Friedman, X. Liu, and M. C. Papaefthymiou, " Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits," Proceedings of the Design Automation and Test in Europe (DATE) Conference, pp. 643-649, March 1999.

  156. R. M. Secareanu, I. S. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, and E. G. Friedman, " Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 314-317, February 1999.

  157. Y. I. Ismail and E. G. Friedman, " Inductance Effects in RLC Trees," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 56-59, February 1999.

  158. K. T. Tang and E. G. Friedman, " Crosstalk Between Loosely Coupled Interconnect," Proceedings of the IEEE 22nd Annual EDS/CAS Activities in Western New York Conference, pp. 9-10, November 1998.

  159. M. C. Papaefthymiou, E. G. Friedman, and X. Liu, " Retiming and Clock Scheduling for High-Performance Synchronous Circuits," Proceedings of the Eighth International Workshop on Power and Timing Modeling, Optimization, and Simulation, pp. 255-264, October 1998.

  160. Y. I. Ismail and E. G. Friedman, " Optimum Repeater Insertion Based on CMOS Delay Model for On-Chip RLC Interconnect," Proceedings of the IEEE International ASIC Conference, pp. 369-373, September 1998.

  161. R. M. Secareanu and E. G. Friedman, " A High Speed CMOS Buffer for Driving Large Capacitive Loads in Digital ASICs," Proceedings of the IEEE International ASIC Conference, pp. 365-368, September 1998.

  162. V. Adler and E. G. Friedman, " Optimizing RC Tree Delay in High Speed ASICs Through Repeater Insertion," Proceedings of the IEEE International ASIC Conference, pp. 375-378, September 1998.

  163. V. Adler and E. G. Friedman, " A Repeater Timing Model and Insertion Algorithm to Reduce Delay in RC Tree Structures," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 2.67-2.70, September 1998.

  164. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Transient Power in CMOS Gates Driving LC Transmission Lines," Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp. 1.337-1.340, September 1998.

  165. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Power Dissipated by CMOS Gates Driving Lossless Transmission Lines," Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 139-141, August 1998.

  166. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Figures of Merit to Characterize the Importance of On-Chip Inductance," Proceedings of the ACM/IEEE Design Automation Conference, pp. 560-565, June 1998.

  167. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Performance Criteria for Evaluating the Importance of On-Chip Inductance," Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. II, pp. 244-247, June 1998.

  168. Y. I. Ismail, E. G. Friedman, and J. L. Neves, " Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines," Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 39-44, February 1998.

  169. I. S. Kourtev and E. G. Friedman, " Topological Synthesis of Clock Trees with Non-Zero Clock Skew," Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 158-163, December 1997.

  170. V. Adler and E. G. Friedman, " Repeater Insertion to Reduce Delay and Power in RC Tree Structures," Proceedings of the Asilomar Conference on Signals, Systems, and Computers, pp. 749-752, November 1997.

  171. I. S. Kourtev and E. G. Friedman, " Topological Synthesis of Clock Trees for VLSI-Based DSP Systems," Proceedings of the IEEE Workshop on Signal Processing Systems, pp. 151-162, November 1997.

  172. R. M. Secareanu and E. G. Friedman, " A CMOS Current Mirror/Divider for High Precision Applications," Proceedings of the IEEE 21st Annual EDS/CAS Activities in Western New York Conference, p. 11, November 1997.

  173. I. S. Kourtev and E. G. Friedman, " The Automated Synthesis of High Performance Clock Distribution Networks," Proceedings of the IEEE International Workshop on Clock Distribution Networks Design, Synthesis, and Analysis, pp. 11-12 (abstract), October 1997.

  174. K. Gaj, E. G. Friedman, and M. J. Feldman, Timing of Large RSFQ Digital Circuits," Proceedings of the 6th International Superconductive Electronics Conference, pp. 299-301, June 1997.

  175. K. Gaj, E. G. Friedman, and M. J. Feldman, "Two-phase Clocking for Medium to Large RSFQ Circuits," Proceedings of the 6th International Superconductive Electronics Conference, pp. 302-304, June 1997.

  176. I. S. Kourtev and E. G. Friedman, " Simultaneous Clock Scheduling and Buffered Clock Tree Synthesis," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1812-1815, June 1997.

  177. V. Adler and E. G. Friedman, " Repeater Design to Reduce Delay and Power in Resistive Interconnect," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2148-2151, June 1997.

  178. K. Gaj, E. G. Friedman, and M. J. Feldman, Choice of the Optimum Timing Scheme for RSFQ Digital Circuits," Proceedings of the 5th International Workshop on High-Temperature Superconducting Electron Devices, pp. 39-40, May 1997.

  179. V. Adler and E. G. Friedman, " Timing and Power Models for CMOS Repeaters Driving Resistive Interconnect," Proceedings of the IEEE ASIC Conference, p. 201-204, September 1996.

  180. E. G. Friedman and J. H. Mulligan, Jr., " Ramp Input Response of RC Tree Network," Proceedings of the IEEE ASIC Conference, pp. 63-66 , September 1996.

  181. K. Gaj, C. H. Cheah, E. G. Friedman, and M. J. Feldman, " Optimal Clocking Design for Large RSFQ Circuits Using Verilog HDL," Proceedings of the Applied Superconductivity Conference, p. 148 (abstract), August 1996.

  182. Q. P. Herr, N. Vukovic, C. Mancini, K. Gaj, Q. Ke, V. Adler, E. G. Friedman, A. Krasniewski, M. F. Bocko, and M. J. Feldman, " Development and Testing of a Four-Bit RSFQ Multiplier-Accumulator," Proceedings of the Applied Superconductivity Conference, p. 149 (abstract), August 1996.

  183. V. Adler, C. H. Cheah, K. Gaj, D. K. Brock, and E. G. Friedman, " A Cadence-Based Design Environment for Single Flux Quantum Circuits," Proceedings of the Applied Superconductivity Conference, p. 157 (abstract), August 1996.

  184. E. G. Friedman, " Research in High Speed, Low Power Synchronous Digital and Mixed-Signal Systems," Proceedings of the Workshop on Academic Electronics in New York State, pp. 207-220, June 1996.

  185. V. Adler and E. G. Friedman, " Delay and Power Expressions for Short-Channel CMOS Inverters Driving Resistive Interconnect," Proceedings of the Workshop on Academic Electronics in New York State, pp. 39-46, June 1996.

  186. J. L. Neves and E. G. Friedman, " Optimal Clock Skew Scheduling Tolerant to Process Variations," Proceedings of the ACM/IEEE Design Automation Conference, pp. 623-628, June 1996.

  187. M. D. Hahm, E. G. Friedman, and E. L Titlebaum, " Analog vs. Digital: A Comparison of Circuit Implementations for Low-Power Matched Filters," Proceedings of the IEEE Symposium on Circuits and Systems, pp. 280-283, May 1996.

  188. V. Adler and E. G. Friedman, " Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load," Proceedings of the IEEE Symposium on Circuits and Systems, pp. 101-104, May 1996.

  189. B. S. Cherkauer and E. G. Friedman, " A Hybrid Radix-4/Radix-8 Low Power, High Speed Multiplier Architecture for Wide Bit Widths," Proceedings of the IEEE Symposium on Circuits and Systems, pp. 53-56, May 1996.

  190. J. L. Neves and E. G. Friedman, " Reduced Sensitivity of Clock Skew Scheduling to Technology Variations," Proceedings of the ACM/SIGDA Physical Design Workshop, pp. 241-248, April 1996.

  191. M. Hahm, E. G. Friedman, and E. Titlebaum, " Receiver Power Issues Related to Matched Filter Implementation for Portable Wireless Communication Terminals," Proceedings of the IEEE Wireless Communication System Symposium, pp. 211-216, November 1995.

  192. J. L. Neves and E. G. Friedman, " Buffered Clock Tree Synthesis with Optimal Clock Skew Scheduling for Reduced Sensitivity to Process Parameter Variations," Proceedings of the TAU'95 ACM/SIGDA International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 131-141, November 1995.

  193. V. Adler and E. G. Friedman, " A Delay Expression for a Short-Channel CMOS Inverter Driving a Resistive-Capacitive Load," Proceedings of the IEEE Nineteenth Annual Electron Devices Activities in Western New York Conference, p. 18, November 1995.

  194. J. L. Neves and E. G. Friedman, " Minimizing Power Dissipation in Non-Zero Skew-based Clock Distribution Networks," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1576-1579, May 1995.

  195. T. Soyata, E. G. Friedman, and J. H. Mulligan, Jr., " Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1748-1751, May 1995.

  196. E. G. Friedman, " Low Power versus High Speed: Can you have both?," Proceedings of the IEEE/ACM Fifth Great Lakes Symposium on VLSI, p. xv, March 1995.

  197. T. Soyata and E. G. Friedman, " Retiming with Non-Zero Clock Skew, Variable Register, and Interconnect Delay," Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 234-241, November 1994.

  198. V. Adler and E. G. Friedman, " A Design Environment for Single Flux Quantum Circuits," Proceedings of the IEEE Eighteenth Annual Electron Devices Activities in Western New York Conference, p. 10, November 1994.

  199. T. Soyata and E. G. Friedman, " Synchronous Performance and Reliability Improvement in Pipelined ASICs," Proceedings of the IEEE ASIC Conference, pp. 383-390, September 1994.

  200. J. L. Neves and E. G. Friedman, " Synthesizing Distributed Buffer Clock Trees for High Performance ASICs," Proceedings of the IEEE ASIC Conference, pp. 126-129, September 1994.

  201. B. S. Cherkauer and E. G. Friedman, " Tapered Buffers for Gate Array and Standard Cell Circuits," Proceedings of the IEEE ASIC Conference, pp. 96-99, September 1994.

  202. B. S. Cherkauer and E. G. Friedman, " Design of Tapered Serial Chains for Reduced Delay and Power Dissipation," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 29-32, August 1994.

  203. B. S. Cherkauer and E. G. Friedman, " A Design Methodology for Low Power, Reduced Area, Reliable CMOS Buffers," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 11-14, August 1994.

  204. J. L. Neves and E. G. Friedman, " Circuit Synthesis of Clock Distribution Networks based on Non-Zero Clock Skew," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 4.175-4.178, May/June 1994.

  205. B. S. Cherkauer and E. G. Friedman, " Unification of Speed, Power, Area, and Reliability in CMOS Tapered Buffer Design," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 4.111-4.114, May/June 1994.

  206. E. G. Friedman, S. M. Kang, E. A. Vittoz, D. J. Allstot, E. P. Harris, and R.-H. Yan, " From 100 Milliwatts/MIPS to 10 Microwatts/MIPS," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 4.1-4.6, May/June 1994.

  207. J. L. Neves and E. G. Friedman, " Topological Design of Clock Distribution Networks based on Non-Zero Clock Skew Specifications," Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 468-471, August 1993.

  208. B. S. Cherkauer and E. G. Friedman, " The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2110-2113, May 1993.

  209. T. Soyata, E. G. Friedman, and J. H. Mulligan, Jr., " Integration of Clock Skew and Register Delays into a Retiming Algorithm," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1483-1486, May 1993.

  210. E. G. Friedman, " Clock Distribution Design in VLSI Circuits - an Overview," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1475-1478, May 1993.

  211. E. G. Friedman, " Minimum Latch Time and Metastable Onset in CMOS Bistable Registers," Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, pp. 442-447, December 1992.

  212. E. G. Friedman, " The Application of Localized Clock Distribution Design to Improving the Performance of Retimed Sequential Circuits," Proceedings of the IEEE Asia-Pacific Conference on Circuits and Systems, pp. 12-17, December 1992.

  213. B. S. Cherkauer and E. G. Friedman, " Power Dissipation of Tapered Serially Connected MOSFETs," Proceedings of the IEEE Sixteenth Annual Electron Devices Activities in Western New York Conference, p. 11, November 1992.

  214. E. G. Friedman, " The Limiting Performance of a CMOS Bistable Register Based on Waveform Considerations," Proceedings of the IEEE 35th Midwest Symposium on Circuits and Systems, pp. 130-133, August 1992.

  215. (E.) G. Friedman and R. M. Lea, " Radiation-Hard Associative String Processors - a High Density Scalable SIMD Architecture," Proceedings of the International Conference on Computing in High Energy Physics '91, Frontiers Science Series No. 3, Y. Watase and F. Abe (Eds.), Tokyo, Japan: Universal Academy Press, Inc., 1991, pp. 223-228.

  216. G. A. Antcliffe, E. G. Friedman, J. R. Hall, and G. H. Hershman, " SOS/CMOS Technology for Space Applications," Proceedings of Government Microcircuit Applications Conference, pp. 157-159, November 1990.

  217. W. L. Marking, S. R. Powell, R. R. Siviy, W. S. Kephart, and E. G. Friedman, " A 150-MHz 1.25 um CMOS/SOS DSP Integrated Circuit," Proceedings of IEEE SOS/SOI Technology Conference, pp. 105-106, October 1989.

  218. G. Yacoub and E. G. Friedman, " An Environment Sensitive Circuit Design Technique for Modeling VLSI Interconnect Impedances," Proceedings of Government Microcircuit Applications Conference, pp. 391-394, October 1987.

  219. E. Friedman et al., "A Signal Tracking Chip Utilizing a VHSIC CMOS/SOS Structured Custom Design Methodology," Proceedings of Government Microcircuit Applications Conference, pp. 217-222, November 1986.

  220. E. Friedman, " A Partitionable Clock Distribution System for Sequential VLSI Circuits," Proceedings of IEEE International Symposium on Circuits and Systems, pp. 743-746, May 1986.

  221. E. Friedman, W. Marking, E. Iodice, and S. Powell, " Parameterized Buffer Cells Integrated into an Automated Layout System," Proceedings of IEEE Custom Integrated Circuits Conference, pp. 389-392, May 1985.

  222. S. Powell, E. Iodice, and E. Friedman, " An Automated, Low Power, High Speed Complementary PLA Design System for VLSI Applications," Proceedings of IEEE International Conference on Computer Design, pp. 314-319, October 1984.

Workshop Presentations
  1. E. G. Friedman, " Design Challenges in High Performance Three-Dimensional Circuits," Keynote Presentation, ACM/IEEE Great Lakes Symposium on VLSI, Boston, Massachusetts, May 11, 2009.

  2. E. G. Friedman, " Interconnect-Based Design Challenges in High Performance Three-Dimensional Circuits," Keynote Presentation, IFIP/IEEE VLSI - SOC Conference, Rhodos, Greece, October 13, 2008.

  3. E. G. Friedman, "Three-Dimensional Integrated Circuits," Interconnection Networks Workshop, San Jose, California, July 22, 2008.

  4. E. G. Friedman, " Physical Design Issues and Technology Trends in Networks-on-Chip," Invited Presentation, 2nd Workshop on Dignostic Services in Network-on-Chips - Test, Debug, and On-Line Monitoring (DSNOC '08), in conjunction with the ACM/IEEE Design Automation Conference, Anaheim, California, June 9, 2008.

  5. E. G. Friedman, " Predictions, Challenges, and Opportunities in CMOS Compatible On-Chip Optical Interconnect, Invited Presentation, Science and Technology Expert Partnership (STEP) Conference on Optical Computer Developments, McLean, Virginia, April 10, 2008.

  6. E. G. Friedman, " Research Challenges in High Performance VLSI/SoC Circuits and Systems," Keynote Presentation, TENCON, IEEE Region 10 Conference, Taipei, Taiwan, October 2007.

  7. E. G. Friedman, "Tech Transfer Incentives - A Successful CEIS Model," Frontiers in Optics, 90th OSA Annual Meeting, Rochester, New York, October 2006.

  8. D. H. Albonesi, P, M. Fauchet, and E. G. Friedman, " Optical Interconnect," DARPA Intra-Chip Communications Workshop, Arlington, Texas, March 2006.

  9. E. G. Friedman, "On-Chip Interconnect: The Past, Present, and Future," Workshop on Future Interconnects and Networks on Chip, Design, Automation & Test in Europe Conference, Munich, Germany, March 2006.

  10. E. G. Friedman, "Research and Technology Transfer in High Performance Integrated Circuit Design," Fourth Annual Microelectronics Design Conference, Rochester, New York, January 2005.

  11. E. G. Friedman, "Research in High Performance Integrated Circuit Design," Third Annual New York State Conference on Microelectronics Design, New York, New York, January 2004.

  12. E. G. Friedman, "High Performance Digital and Mixed-Signal Integrated Circuit Design," Second Annual New York State Conference on Microelectronics Design, Rochester, New York, January 2003.

  13. E. G. Friedman, "High Performance VLSI/IC Design and Analysis Laboratory," First Annual New York State Conference on Microelectronics Design, New York, New York, January 2002.

  14. E. G. Friedman, "Substrate Coupling and Interconnect Noise in Mixed-Signal and High-Speed Digital ICs," IEEE CAS Workshop on Mixed-Signal Integrated Circuit Design, Long Beach, California, December 1999.

  15. E. Friedman and N. Bindal, "Challenges in Clock Distribution Networks," ACM International Symposium on Physical Design, Monterey, California, April 1999.

  16. E. G. Friedman,"Designing a High Performance Digital Signal Processor," IEEE Physical Design Workshop on Module Generation and Silicon Compilation, Long Beach, California, May 1989.

  17. E. G. Friedman, "A Hierarchical Design Technique for Minimizing Clock Skew in VLSI Circuits," IEEE Physical Design Conference, Austin, Texas, March 1986.

  18. E. G. Friedman, W. Marking, E. Iodice, and S. Powell, "Generating Parameterized Cells Using Application Specific Feedback," IEEE Physical Design Workshop, January 1985.

  19. E. G. Friedman, G. Yacoub, and S. Powell, "A Hierarchical VLSI Design System for Synthesizing CMOS/SOS Integrated Circuits," IEEE SOS/SOI Technology Workshop, October 1984.

  20. E. G. Friedman and G. Yacoub, "A Two Level Metal, Software Compatible, CMOS/SOS Gate Array Family," IEEE SOS/SOI Technology Workshop, Jackson Hole, Wyoming, October 1983.

Professional Status Reports
  1. S. Srinivasan and E. G. Friedman, " System Synchronization Styles and Trends," EE Times Online, March 6, 2006.

  2. E. G. Friedman, " What are clock distribution networks?," ACM/SIGDA E-Newsletter, Vol. 35, No. 23, December 1, 2005, Also in Wikipedia, under Clock Distribution Networks.

  3. Y. I. Ismail and E. G. Friedman, " Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits: A Summary," IEEE Circuits and Systems Magazine, Volume 3, Number 1, pp. 24-28, First Quarter 2003.

  4. E. G. Friedman, "Editorial," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 10, No. 6, pp. 681-682, December 2002.

  5. E. G. Friedman and W. Wolf, "Upcoming Changes to TVLSI," IEEE Circuits and Systems Society Newsletter, Volume 10, Number 4, p. 47, December 1999.

  6. E. G. Friedman, " On-Chip Interconnect Noise in Deep Submicrometer CMOS Integrated Circuits," IEEE Circuits and Systems Society Newsletter, Volume 10, Number 3, pp. 16-21, 29, September/October 1999.

  7. E. G. Friedman, "Committee Report VLSI Systems and Applications Technical Committee," IEEE Circuits and Systems Society Newsletter, Volume 8, Number 3, pp. 13,16, September 1997.

  8. E. Friedman, "ED Rochester Chapter," IEEE Electron Devices Society Newsletter, Vol. 3, No. 1, pp. 11-12, January 1996. Also, "Chapter Report Electron Device Society - Progress Report for 1995," The Rochester Engineer, p. 12, March 1996.

  9. E. Friedman and B. Sheu, "VSA Technical Committee," IEEE Circuits and Systems Society Newsletter, Volume 6, Number 3, p. 7, September 1995.

Dissertation
    E. G. Friedman, Performance Limitations in Synchronous Digital Systems, University of California, Irvine, California, June 1989. Abstract published in Dissertations Abstracts International, Volume 50, Number 7, pp. 3067-B, January 1990. Advisor: Professor James H. Mulligan, Jr.