Summary of Recent Research Topics

Eby G. Friedman

Distinguished Professor of Electrical and Computer Engineering
Department of Electrical and Computer Engineering
University of Rochester
Rochester, New York 14627
USA

High Performance Digital and Analog VLSI/ICs
The focus of this research is the design and analysis of high performance digital and analog integrated circuits, and supporting design techniques, methodologies, CAD tools, and circuit structures. Speed, area, power dissipation, and reliability tradeoffs in CMOS technology are investigated in terms of application-specific constraints and their fundamental circuit level limitations. The general approach is to apply analog signal concepts to the design and analysis of VLSI systems to maximize both circuit and system level performance while satisfying the complexity requirements inherent to the VLSI environment.

On-Chip Interconnect and Substrate Coupling Noise
Interconnect and substrate coupling noise have become issues of primary concern in high speed digital and mixed-signal integrated circuits. In order to ascertain whether a section of interconnect should be modeled as either an RC or an RLC impedance, figures of merit are being developed to determine how best to model both a line and a tree. Closed form solutions characterizing the propagation delay, rise time, overshoots, and settling time of signals in an RLC tree and the peak coupling noise voltage (or crosstalk) between adjacent RLC interconnect are also under development. Substrate coupling between high current analog devices and digital latches is under investigation based on simulation and extensive data derived from experimental test circuits. The focus of these research efforts is on interpreting, designing, and compensating for the effects of RLC interconnect and substrate impedances rather than extraction and simulation algorithms. Particular effort is being placed on the on-chip global signals, such as the clock and power distribution networks and the interactions of these networks with the substrate, neighboring interconnect, and the on-chip decoupling capacitors.

Automated Synthesis of High Performance Clock Distribution Networks
Most ULSI/VLSI-based systems utilize fully synchronous timing, requiring a globally distributed clock signal as a temporal reference signal to control the sequence of operations. This high speed clock signal must be distributed to every register at a precise time. The focus of this research is the automated synthesis of high speed, highly reliable clock distribution networks. A four phase top-down design system is under development for synthesizing buffered clock distribution networks. This capability will be developed as an integrated synthesis system, validated with benchmark circuits, and tested with manufactured demonstration circuits.

Circuit Design Techniques for Driving RLC Interconnect
Interconnect impedances have become the predominant source of delay in deep submicrometer CMOS circuits. The interaction between the active CMOS transistors and the passive interconnect is a fundamental issue in the design of high performance VLSI-based systems. Furthermore, the interconnect structure propagating high speed signals over long distances is properly modeled as an RLC transmission line. The focus of this research effort is on the development of closed form and accurate analytic expressions that describe the interaction between the CMOS circuits and the interconnect impedances loading these transistors. These expressions are applied to the development of VLSI-based design methodologies for driving these RC and RLC interconnect impedances.

Integrated Pipelining, Retiming, and Clock Scheduling
For the optimal behavioral synthesis of a synchronous system, the processes of pipelining, retiming, and clock skew scheduling must be implemented in an integrated fashion. Physically accurate algorithms are being developed to more efficiently synthesize these high performance synchronous systems. These results will provide a systematic procedure for building high performance recursively structured pipelined systems and related clock distribution networks.

Design of MSI/LSI Circuits Based on Innovative Technologies
Specialized circuits using aggressive niche technologies are developed by applying innovative design techniques and specialized CAD tools. This research area requires a merging of a materials/device background with practical circuit design issues when building extremely high performance systems (i.e., high speed, low power, mixed signals, low noise.)