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ECE

U of R

Increasing reliance on computing as a means of scientific exploration demands ever higher speed, reliability, and efficiency from high-performance systems. Achieving sustained gain in all these metrics requires continued innovation in processor microarchitecture, the communication and coherency substrate, and the underlying device technology. Such innovation builds upon concrete understanding of the interaction of these components. Our research spans these components and focuses on delivering practical, complexity-effective solutions. In addition to architectural exploration, we are also investigating how to leverage new technologies and circuit techniques. For example, we are investigating the use of on-chip optics, spin-based devices, and high-speed communication circuitry. At the same time, architecture design is also driven by the demand of software. We are also interested in deepening the understanding of the behavior of real-world applications. For example, we are working with physicists who use computational means to study inertial confinement fusion.

Michael Huang received the BS degree in computer science and engineering from Tsinghua University, Beijing, in 1994, the MS and the PhD degree in computer science from University of Illinois at Urbana-Champaign in 1999 and 2002, respectively. From 1994 to 1997, he was a lead architect in building a 32-processor hierarchical shared-memory multiprocessor research prototype. He joined the faculty of the Electrical and Computer Engineering department in 2002.

His research interests include various aspects of high-performance computer architecture such as processor microarchitecture, communication and memory substrate, reliability, and energy-efficient and complexity-effective design. His is particularly interested in addressing emerging issues and exploring new capabilities in the underlying device, circuit, and manufacturing technology. He is a recipient of the NSF CAREER award and a member of the IEEE and the ACM.

MICRO’08

“A Performance-Correctness Explicitly-Decoupled Architecture”,  A. Garg and M. Huang, in Proc. of the 41st Int’l Symp. on Microarchitecture, Nov. 2008

HPCA’08

“Supporting Highly-Decoupled Thread-Level Redundancy for Parallel Programs”, M. Rashid and M. Huang, in Proc. of the 14th Int’l Symp. on High-Performance Computer Architecture, Feb. 2008

ISCA’06

“Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification”, A. Garg, M. Rashid, and M. Huang, in Proc. of the 33rd Int’l Symp. on Computer Architecture, June 2006