Workshop on Complexity-Effective Design

(tools and techniques to support high performance and power- and verification-aware design)

June 10, 2000
Vancouver, B.C.

To be held in conjunction with the 27th International Symposium on Computer Architecture (ISCA 27)

Organizers:

David H. Albonesi
University of Rochester
albonesi@ece.rochester.edu

Pradip Bose
IBM T. J. Watson Research Center
pbose@us.ibm.com

Subbarao Palacharla
Intel Corporation
subbarao@ichips.intel.com

Scope:

Complex hardware and software techniques for exploiting ILP and memory locality may have a widely varying impact, significantly benefiting some application domains while having little (or even detrimental) net effect on others. Furthermore, growing transistor budgets coupled with the continuing drive for higher clock frequencies and time-to-market pressures create the potential for power dissipation or verification time to limit chip functionality in future systems. Thus, design techniques and methodologies are needed at the microarchitecture, software, and system levels that

improve energy efficiency;
reduce verification time;
better tailor hardware and software resources to application requirements to reduce power and/or improve performance;
properly balance clock speed and the exploitation of ILP and memory locality in order to maximize performance;
ensure scalable performance growth within a given microarchitecture generation.

The goal of this workshop is to provide a forum for microarchitects, performance modelers, compiler developers, verification experts, and system designers to discuss and explore such hardware/software techniques and tools for complexity-effective (CE) computation.

Topics for talks include, but are not limited to:

Instruction set architecture issues in CE design
- RISC vs. VLIW/EPIC
- virtual architectures
- programmable architectures
Characterization of workloads in terms of energy-performance variations
Analytical models for power-performance or performance-verifiability tradeoffs
- scalability analysis
- bounds (limit-study) models
- complexity analysis
Processor/system simulators with built-in energy models
Microarchitectures to support CE system design
- application-driven dynamic control and adaptation of on-chip resources
- design for verification ideas in microarchitecture design
- power-aware design principles
- cache and memory hierarchy designs to support CE processing
- distributed/decoupled control architectures
- CE characterization and comparison of different paradigms
  - multicluster superscalar machines
  - VLIW
  - vector machines
  - chip multiprocessors (CMP)
  - multiscalar and trace processors
  - multithreading including SMT
  - merged DRAM-Logic, IRAM or PIM architectures
  - reconfigurable architectures
  - asynchronous and gated-clock design approaches
  - embedded, special purpose and network processors
Compiler and operating system support for CE processing
- selection, scheduling and register allocation issues in energy-efficiency
- profile-driven optimization for CE support
- cache blocking and code/data layout optimization in CE designs
- compiler support for future/emerging CE microarchitecture paradigms
Algorithm and application tuning for power-performance efficiency
Newer metrics for power-performance efficiency and "verifiability"

Program Committee:

Dave Albonesi, University of Rochester
Todd Austin, University of Michigan
Pradip Bose, IBM Watson
George Cai, Intel
Srilatha Manne, Compaq
Margaret Martonosi, Princeton University
Subbarao Palacharla, Intel
Jim Smith, University of Wisconsin

Schedule:

Submission deadline (5-10 page extended abstract in postscript or PDF format emailed to any of the co-chairs): May 1, 2000
Acceptance notification: May 15, 2000
Final version due: June 1, 2000

Workshop proceedings will be distributed. A post-workshop special issue (IEEE Micro) is planned.