Final Program

Organizers:
David H. Albonesi
University of Rochester
albonesi@ece.rochester.edu

Pradip Bose
IBM T. J. Watson Research Center
pbose@us.ibm.com

Diana Marculescu
Carnegie-Mellon University
dianam@ece.cmu.edu

Scope:
The quest for higher performance via deep pipelining (for high clock rate) and speculative, out-of-order execution (for high IPC) has yielded processors with greater performance, but at the expense of much greater design complexity. The costs of higher complexity are many-fold, including increased verification time, higher power dissipation, and reduced scalability with microarchitectural resource size parameters and process shrinks. The goal of this workshop is to provide a forum for microarchitects, circuit designers, performance modelers, compiler developers, verification experts, and system designers to discuss and explore hardware/software techniques and tools for creating future designs that are more complexity-effective (CE).

For the purposes of this workshop, a CE design feature or tool either (a) yields a significant performance and/or power efficiency improvement relative to the increase in hardware/software complexity incurred; or (b) significantly reduces complexity (design time and/or verification time and/or improved scalability and/or power consumption) with a tolerable performance impact. Please refer to the sample review article by the workshop organizers for a detailed discussion (with examples) of CE design. In presenting this workshop for the third time, we hope to focus it more on the following topics:

• Metrics for establishing the CE of a given design. Scalability criteria and evaluation. Quantifying verification complexity. Power-performance metrics.
• Characterization of current and emerging workloads to help determine the CE value of alternate design paradigms.
• The merits of different architectural approaches (ooo versus in-order superscalar, VLIW/EPIC, clustered microarchitectures, chip multiprocessor, multithreading, multi-clock, GALS and asynchronous architectures, etc.) in terms of their CE.
• Comparison of these approaches in terms of CE using new or established metrics.
• Case studies of actual designs in which CE was taken into account.
• Pipeline depth and CE issues, including "helper" pipeline approaches.
• Analytical models for power-performance or performance-verifiability tradeoffs.
• Design-for-verification architectures.
• Impact of clock- and Vdd-gating on verification and reliability in power-aware designs.
• Approaches to improving power-efficiency without unduly increasing design complexity.
• Microarchitectures that scale effectively with process shrinks/variations.
• Complexity-effective cache and memory hierarchy design.
• Compiler and operating system support for CE, e.g., moving functionality to software in order to reduce overall design complexity.

• Dave Albonesi, University of Rochester
• Todd Austin, University of Michigan
• Iris Bahar, Brown University
• Pradip Bose, IBM Watson
• George Cai, Intel
• Babak Falsafi, CMU
• Keith Farkas, Compaq
• Antonio Gonzalez, UPC
• Peter Hofstee, IBM
• Diana Marculescu, CMU
• Margaret Martonosi, Princeton University
• Gokhan Memik, UCLA
• Subbarao Palacharla, Sanera Systems
• Jim Smith, University of Wisconsin

A post-workshop proceedings, containing abstracts, full papers, and/or talk slides, will be distributed, and a special issue of IEEE Computer or IEEE Micro, based on selected talks presented at the workshop, is planned.