To be held in conjunction with the 30th International Symposium on Computer
Architecture (ISCA 30)
Potential authors may also want to consider sending a modified version of their submission to the IEEE Micro Special Issue on Power- and Complexity-Aware Design
David H. Albonesi
University of Rochester
IBM T. J. Watson Research Center
The quest for higher performance via deep pipelining (for high clock rate) and speculative, out-of-order execution (for high IPC) has yielded processors with greater performance, but at the expense of much greater design complexity. The costs of higher complexity are many-fold, including increased verification time, higher power dissipation, and reduced scalability with microarchitectural resource size parameters and process shrinks. The goal of this workshop is to provide a forum for microarchitects, circuit designers, performance modelers, compiler developers, verification experts, and system designers to discuss and explore hardware/software techniques and tools for creating future designs that are more complexity-effective (CE).
For the purposes of this workshop, a CE design feature or tool either (a) yields a significant performance and/or power efficiency improvement relative to the increase in hardware/software complexity incurred; or (b) significantly reduces complexity (design time and/or verification time and/or improved scalability and/or power consumption) with a tolerable performance impact. Please refer to the sample review article by the workshop organizers for a detailed discussion (with examples) of CE design. In presenting this workshop for the fourth time, we hope to focus it more on the following topics:
A post-workshop proceedings, containing abstracts, full papers, and/or talk slides, will be distributed.