bhardwaj@[ece,cs].rochester.edu

Graduate Student, Department of Electrical and Computer Engineering

School of Engineering and Applied Sciences

University of Rochester, NY 14627

RESUME(pdf|doc)

What's New

• Writing M.S Thesis under Prof. Sandhya Dwarkadas and Prof. Michael C. Huang
  
• Back from Summer Internship'07 at Intel, Santa Clara
  
• Masters Student at University of Rochester, started in Fall'06
  

• Multi-Core Architecture
  
• Memory Ordering, Cache Coherence Protocols
• Memory Hierarchy Design
• Validation Architecture and Tools

• Graduate Technical Intern, Intel Technologies, Santa Clara (June'07 - August'07)
• Developed test generator for cache coherence protocol RTL verification
  
• Research Assistance, under Prof Sandhya Dwarkadas and Prof. Michael Huang (August'06 - May'07)
• Coherence protocols and memory hierarchy design for chip multi-processors
  
• CPU System Validation Engineer, Intel Technologies, Bangalore (March'04 - July'06)
• Worked in a team validating Intel's next generation server product based on message based interconnect protocol
• Project Associate, Indian Institute of Technology, Delhi (June-'03 - Feb'04)
• Worked under Prof. M Balakrishnan and Prof. Anshul Kumar  on a Research Project "A methodology for Synthesis of Multi-Processor ASIPs"
• Extending LEON Multiprocessor (LEON-MP) with Local Memory
• Project Assistance: MIPS Emulator, Case Study of ADM-XRC FPGA Board, Floating Point Integration with Leon
  

• CSC 456: Operating Systems
• Assignment1 (Unix Shell)
  
• Assignment2 (Travelling Sales Man Problem)
  
• Assignment3 (Kernel Synchronization Routines)
  
• ECE 401: Advanced Computer Architecture
• ECE 461: Digital Integrated Circuit Design
• ECE 492: VLSI Design Methodologies
• Decoupling Capacitance (Presentation | Area Paper)
  
• CSC 458: Parallel and Distributed Systems
• LockBox Implementation for Fine Grained Hardware Synchronization (Report)
• ECE 495:  Advanced Research in CS/ECE (RA)